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AJvYcCXmS51N0PZJENYWq3osmhfp2YjOj0HkkzIq3gFoSUxnkHDbSCBnfHiLLQW3gwDvc2NE3IDK1wZxDxx7/HTz3TlGsbAyRzcLzUMLCNcDOk2J6vPJOqi9OEIgKJROqcUafxjNbuhj0P2C2NuX+rQFHSDoeCrEfz2ych0UuTIQyW5iRt3NFGWFwv0BxJwG X-Gm-Message-State: AOJu0YyWVCyL2YbLSi0BJHFOoge/kvgzs0fteRwDJ7pjvD5aHxc5QXGw FLfPfiZ7K/tDD1O3ijc6Weh8PwmKn8yBFK4GCPnYBjfvPiSz7OXb X-Received: by 2002:a05:600c:4590:b0:418:f991:713f with SMTP id r16-20020a05600c459000b00418f991713fmr3751wmo.23.1713895163472; Tue, 23 Apr 2024 10:59:23 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:cef0:9ed3:1428:f85f]) by smtp.gmail.com with ESMTPSA id fl5-20020a05600c0b8500b0041abeaaf7f0sm2808145wmb.28.2024.04.23.10.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 10:59:22 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 07/13] pinctrl: renesas: pinctrl-rzg2l: Add function pointer for writing to PMC register Date: Tue, 23 Apr 2024 18:58:54 +0100 Message-Id: <20240423175900.702640-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240423175900.702640-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240423175900.702640-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Lad Prabhakar This patch introduces a function pointer, pmc_writeb(), in the struct rzg2l_pinctrl_data to facilitate writing to the PMC register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_A bit before writing to PMC registers is required, whereas this is not the case for the existing RZ/G2L family. This addition enables the reuse of existing code for RZ/V2H(P). Additionally, this patch populates this function pointer with appropriate data for existing SoCs. Note that this functionality is only handled in rzg2l_gpio_request(), as PMC unlock/lock during PFC setup will be taken care of in the pwpr_pfc_unlock/pwpr_pfc_lock. Signed-off-by: Lad Prabhakar --- RFC->v2 - No change --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 0840fda7ca69..e6d986b84be6 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -260,6 +260,7 @@ struct rzg2l_pinctrl_data { unsigned int n_variable_pin_cfg; void (*pwpr_pfc_unlock)(struct rzg2l_pinctrl *pctrl); void (*pwpr_pfc_lock)(struct rzg2l_pinctrl *pctrl); + void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr); }; /** @@ -463,6 +464,11 @@ static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { }; #endif +static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr) +{ + writeb(val, addr); +} + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -1410,7 +1416,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) /* Select GPIO mode in PMC Register */ reg8 = readb(pctrl->base + PMC(off)); reg8 &= ~BIT(bit); - writeb(reg8, pctrl->base + PMC(off)); + pctrl->data->pmc_writeb(pctrl, reg8, pctrl->base + PMC(off)); spin_unlock_irqrestore(&pctrl->lock, flags); @@ -2701,6 +2707,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { #endif .pwpr_pfc_unlock = &rzg2l_pwpr_pfc_unlock, .pwpr_pfc_lock = &rzg2l_pwpr_pfc_lock, + .pmc_writeb = &rzg2l_pmc_writeb, }; static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -2714,6 +2721,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .hwcfg = &rzg2l_hwcfg, .pwpr_pfc_unlock = &rzg2l_pwpr_pfc_unlock, .pwpr_pfc_lock = &rzg2l_pwpr_pfc_lock, + .pmc_writeb = &rzg2l_pmc_writeb, }; static struct rzg2l_pinctrl_data r9a08g045_data = { @@ -2726,6 +2734,7 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .hwcfg = &rzg3s_hwcfg, .pwpr_pfc_unlock = &rzg2l_pwpr_pfc_unlock, .pwpr_pfc_lock = &rzg2l_pwpr_pfc_lock, + .pmc_writeb = &rzg2l_pmc_writeb, }; static const struct of_device_id rzg2l_pinctrl_of_table[] = { -- 2.34.1