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75f8a8fa-b012-49fe-8bcc-08dc63f89769 X-MS-Exchange-CrossTenant-AuthSource: DS7PR10MB5280.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2024 00:50:52.5433 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ke7ROWxSc7dDyXH6MuoqJnkE4hqecxvL7B2jJdTD2PfzSQDJ6bLtZ5HrKmw/ctafYee5d1EvNBRBJI3mKJ8BX9BBUVKHCGOwXinNenrNBag= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR10MB6689 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-23_20,2024-04-23_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2404240003 X-Proofpoint-GUID: UwCIkDyjfBbj8Nasfd7YZgN5nuCAXu8_ X-Proofpoint-ORIG-GUID: UwCIkDyjfBbj8Nasfd7YZgN5nuCAXu8_ On 4/16/24 14:35, Sean Christopherson wrote: > On Fri, Apr 12, 2024, Chao Gao wrote: >> On Tue, Apr 09, 2024 at 09:31:45PM -0400, Alejandro Jimenez wrote: >>> >>> On 4/9/24 02:45, Chao Gao wrote: >>>>> diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c >>>>> index 4b74ea91f4e6..853cafe4a9af 100644 >>>>> --- a/arch/x86/kvm/svm/avic.c >>>>> +++ b/arch/x86/kvm/svm/avic.c >>>>> @@ -165,8 +165,10 @@ int avic_ga_log_notifier(u32 ga_tag) >>>>> * bit in the vAPIC backing page. So, we just need to schedule >>>>> * in the vcpu. >>>>> */ >>>>> - if (vcpu) >>>>> + if (vcpu) { >>>>> kvm_vcpu_wake_up(vcpu); >>>>> + ++vcpu->stat.ga_log_event; >>>>> + } >>>>> >>>> >>>> I am not sure why this is added for SVM only. >>> >>> I am mostly familiar with AVIC, and much less so with VMX's PI, so this is >>> why I am likely missing potential stats that could be useful to expose from >>> the VMX side. I'll be glad to implement any other suggestions you have. >>> >>> >>> it looks to me GALog events are >>>> similar to Intel IOMMU's wakeup events. Can we have a general name? maybe >>>> iommu_wakeup_event >>> >>> I believe that after: >>> d588bb9be1da ("KVM: VMX: enable IPI virtualization") >>> >>> both the VT-d PI and the virtualized IPIs code paths will use POSTED_INTR_WAKEUP_VECTOR >>> for interrupts targeting a blocked vCPU. So on Intel hosts enabling IPI virtualization, >>> a counter incremented in pi_wakeup_handler() would record interrupts from both virtualized >>> IPIs and VT-d sources. >>> >>> I don't think it is correct to generalize this counter since AMD's implementation is >>> different; when a blocked vCPU is targeted: >>> >>> - by device interrupts, it uses the GA Log mechanism >>> - by an IPI, it generates an AVIC_INCOMPLETE_IPI #VMEXIT >>> >>> If the reasoning above is correct, we can add a VMX specific counter (vmx_pi_wakeup_event?) >>> that is increased in pi_wakeup_handler() as you suggest, and document the difference >>> in behavior so that is not confused as equivalent with the ga_log_event counter. >> >> Correct. If we cannot generalize the counter, I think it is ok to >> add the counter for SVM only. Thank you for the clarification. > > There's already a generic stat, halt_wakeup, that more or less covers this case. I don't think we can extrapolate PI-originated wake ups from halt_wakeup, since it can/will also be triggered with APICv/AVIC disabled. > And despite what the comment says, avic_ga_log_notifier() does NOT schedule in > the task, kvm_vcpu_wake_up() only wakes up blocking vCPUs, no more, no less. True, both the GA log and the PI wake up handler just call kvm_vcpu_wake_up(). > > I'm also not at all convinced that KVM needs to differentiate between IPIs and > device interrupts that arrive when the vCPU isn't in the guest. E.g. this can > kinda sorta be used to confirm IRQ affinity, but if the vCPU is happily running > in the guest, such a heuristic will get false negatives. > > And for confirming that GA logging is working, that's more or less covered by the > proposed APICv stat. If AVIC is enabled, the VM has assigned devices, and GA logging > *isn't* working, then you'll probably find out quite quickly because the VM will > have a lot of missed interrupts, e.g. vCPUs will get stuck in HLT. ACK, if the device interrupts are not being handled correctly there will be lots of complaints during device initialization as we have seen before. There is one scenario in which you can have APICv/AVIC enabled but only doing the IPI acceleration, while device interrupts are still using the legacy path. It requires booting the host kernel with 'amd_iommu_intr=legacy'(AMD) or with 'intremap=nopost'(Intel), so that is a special case since you must explicitly request the behavior. In short, I typically use the GA Log tracepoint to confirm IOMMU AVIC is working as expected, so I wanted to provide the equivalent via the stats. If we want to have a common stat, we could have a pi_wakeup stat that is incremented both in ga_log and vmx_pi_wakeup_event, but I do understand that is not strictly necessary, specially if we want to be conservative with the number of stats. Thank you, Alejandro