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 <20240423120011.21554-1-pshete@nvidia.com>
In-Reply-To: <20240423120011.21554-1-pshete@nvidia.com>
From: Bartosz Golaszewski <brgl@bgdev.pl>
Date: Wed, 24 Apr 2024 10:31:10 +0200
Message-ID: <CAMRc=MfJokORpEOMkOmQdzTuZxcUAcnmpdEyJWKqvT0gCpuzbg@mail.gmail.com>
Subject: Re: [PATCH v2] gpio: tegra186: Fix tegra186_gpio_is_accessible() check
To: Prathamesh Shete <pshete@nvidia.com>
Cc: linus.walleij@linaro.org, jonathanh@nvidia.com, treding@nvidia.com, 
	sfr@canb.auug.org.au, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, 
	linux-kernel@vger.kernel.org, mochs@nvidia.com, csoto@nvidia.com, 
	jamien@nvidia.com, smangipudi@nvidia.com
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On Tue, Apr 23, 2024 at 2:00=E2=80=AFPM Prathamesh Shete <pshete@nvidia.com=
> wrote:
>
> The controller has several register bits describing access control
> information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it
> means we have full read/write access to all the registers for given GPIO
> pin. When SCR_SEC[R|W]EN is set, it means we need to further check the
> accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all
> the registers for given GPIO pin.
>
> This check was previously declaring that a GPIO pin was accessible
> only if either of the following conditions were met:
>
>   - SCR_SEC_REN + SCR_SEC_WEN both set
>
>     or
>
>   - SCR_SEC_REN + SCR_SEC_WEN both set and
>     SCR_SEC_G1R + SCR_SEC_G1W both set
>
> Update the check to properly handle cases where only one of
> SCR_SEC_REN or SCR_SEC_WEN is set.
>
> Fixes: b2b56a163230 ("gpio: tegra186: Check GPIO pin permission before ac=
cess.")
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> ---

No changelog since v1. No Thierry's tag. Please resend.

Bart