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From: Peng Fan <peng.fan@nxp.com>
To: Fabio Aiuto <fabio.aiuto@engicam.com>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh@kernel.org>, Conor
 Dooley <conor+dt@kernel.org>
CC: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"imx@lists.linux.dev" <imx@lists.linux.dev>,
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	<linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>, matteo.lisi <matteo.lisi@engicam.com>, Mirko
 Ardinghi <mirko.ardinghi@engicam.com>
Subject: RE: [PATCH v4 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM
Thread-Topic: [PATCH v4 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM
Thread-Index: AQHaliMGtjTu4L2HCUOD9XlB0g8kD7F3Oulg
Date: Wed, 24 Apr 2024 10:39:14 +0000
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> Subject: [PATCH v4 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM
>=20
> i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
>=20
> Main features:
>=20
> CPU:   NXP i.MX 93
> MEMORY: Up to 2GB LPDDR4
> NETWORKING: 2x Gb Ethernet
> USB: USB OTG 2.0, USB HOST 2.0
> STORAGE: eMMC starting from 4GB
> PERIPHERALS: UART, I2C, SPI, CAN, SDIO, GPIO
>=20
> The i.Core MX93 needs to be mounted on top of Engicam baseboards to work.
>=20
> Add devicetree include file.
>=20
> Cc: Matteo Lisi <matteo.lisi@engicam.com>
> Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../boot/dts/freescale/imx93-icore-mx93.dtsi  | 271 ++++++++++++++++++
>  1 file changed, 271 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
>=20
> diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
> b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
> new file mode 100644
> index 000000000000..32a56d51f904
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
> @@ -0,0 +1,271 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 NXP
> + * Copyright 2024 Engicam s.r.l.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx93.dtsi"
> +
> +/ {
> +	model =3D "Engicam i.Core MX93 SoM";
> +	compatible =3D "engicam,icore-mx93", "fsl,imx93";
> +
> +	reg_vref_1v8: regulator-adc-vref {
> +		compatible =3D "regulator-fixed";
> +		regulator-name =3D "vref_1v8";
> +		regulator-min-microvolt =3D <1800000>;
> +		regulator-max-microvolt =3D <1800000>;
> +	};
> +};
> +
> +&adc1 {
> +	vref-supply =3D <&reg_vref_1v8>;
> +	status =3D "okay";
> +};
> +
> +&eqos {
> +	pinctrl-names =3D "default";
> +	pinctrl-0 =3D <&pinctrl_eqos>;
> +	phy-mode =3D "rgmii-id";
> +	phy-handle =3D <&ethphy1>;
> +	status =3D "okay";
> +
> +	mdio {
> +		compatible =3D "snps,dwmac-mdio";
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		ethphy1: ethernet-phy@7 {
> +			compatible =3D "ethernet-phy-ieee802.3-c22";
> +			reg =3D <7>;
> +		};
> +	};
> +};
> +
> +&fec {
> +	pinctrl-names =3D "default";
> +	pinctrl-0 =3D <&pinctrl_fec>;
> +	phy-mode =3D "rgmii-id";
> +	phy-handle =3D <&ethphy2>;
> +	fsl,magic-packet;
> +	status =3D "okay";
> +
> +	mdio {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		ethphy2: ethernet-phy@7 {
> +			compatible =3D "ethernet-phy-ieee802.3-c22";
> +			reg =3D <7>;
> +		};
> +	};
> +};
> +
> +&lpi2c2 {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <0>;
> +	clock-frequency =3D <400000>;
> +	pinctrl-names =3D "default", "sleep";
> +	pinctrl-0 =3D <&pinctrl_lpi2c2>;
> +	pinctrl-1 =3D <&pinctrl_lpi2c2>;
> +	status =3D "okay";
> +
> +	pmic@25 {
> +		compatible =3D "nxp,pca9451a";
> +		reg =3D <0x25>;
> +		nxp,wdog_b-warm-reset;
> +
> +		interrupt-parent =3D <&gpio2>;
> +		interrupts =3D <15 IRQ_TYPE_LEVEL_LOW>;
> +
> +		regulators {
> +			buck1: BUCK1 {
> +				regulator-name =3D "BUCK1";
> +				regulator-min-microvolt =3D <600000>;
> +				regulator-max-microvolt =3D <2187500>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay =3D <3125>;
> +			};
> +
> +			buck2: BUCK2 {
> +				regulator-name =3D "BUCK2";
> +				regulator-min-microvolt =3D <600000>;
> +				regulator-max-microvolt =3D <2187500>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay =3D <3125>;
> +			};
> +
> +			buck4: BUCK4{
> +				regulator-name =3D "BUCK4";
> +				regulator-min-microvolt =3D <600000>;
> +				regulator-max-microvolt =3D <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck5: BUCK5{
> +				regulator-name =3D "BUCK5";
> +				regulator-min-microvolt =3D <600000>;
> +				regulator-max-microvolt =3D <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck6: BUCK6 {
> +				regulator-name =3D "BUCK6";
> +				regulator-min-microvolt =3D <600000>;
> +				regulator-max-microvolt =3D <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo1: LDO1 {
> +				regulator-name =3D "LDO1";
> +				regulator-min-microvolt =3D <1600000>;
> +				regulator-max-microvolt =3D <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo2: LDO2 {
> +				regulator-name =3D "LDO2";
> +				regulator-min-microvolt =3D <800000>;
> +				regulator-max-microvolt =3D <1150000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo3: LDO3 {
> +				regulator-name =3D "LDO3";
> +				regulator-min-microvolt =3D <800000>;
> +				regulator-max-microvolt =3D <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo4: LDO4 {
> +				regulator-name =3D "LDO4";
> +				regulator-min-microvolt =3D <800000>;
> +				regulator-max-microvolt =3D <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo5: LDO5 {
> +				regulator-name =3D "LDO5";
> +				regulator-min-microvolt =3D <1800000>;
> +				regulator-max-microvolt =3D <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
> +&usdhc1 {
> +	pinctrl-names =3D "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 =3D <&pinctrl_usdhc1>;
> +	pinctrl-1 =3D <&pinctrl_usdhc1>;
> +	pinctrl-2 =3D <&pinctrl_usdhc1>;
> +	bus-width =3D <8>;
> +	non-removable;
> +	status =3D "okay";
> +};
> +
> +&usdhc2 {/*SD Card*/
> +	pinctrl-names =3D "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-1 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-2 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>;
> +	bus-width =3D <4>;
> +	no-1-8-v;
> +	max-frequency =3D <25000000>;
> +	status =3D "okay";
> +};
> +
> +&iomuxc {
> +
> +	pinctrl_eqos: eqosgrp {
> +		fsl,pins =3D <
> +			MX93_PAD_ENET1_MDC__ENET_QOS_MDC
> 0x53e
> +			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO
> 0x53e
> +			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0
> 0x53e
> +			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1
> 0x53e
> +			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2
> 0x53e
> +			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3
> 0x53e
> +
> 	MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_C
> LK  0x53e
> +
> 	MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL            0x53e
> +			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0
> 0x53e
> +			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1
> 0x53e
> +			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2
> 0x53e
> +			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3
> 0x53e
> +
> 	MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_C
> LK  0x53e
> +
> 	MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL            0x53e
> +		>;
> +	};
> +
> +	pinctrl_fec: fecgrp {
> +		fsl,pins =3D <
> +			MX93_PAD_ENET2_MDC__ENET1_MDC
> 0x57e
> +			MX93_PAD_ENET2_MDIO__ENET1_MDIO
> 0x57e
> +			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0
> 0x57e
> +			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1
> 0x57e
> +			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2
> 0x57e
> +			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3
> 0x57e
> +			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC
> 0x5fe
> +			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL
> 0x57e
> +			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0
> 0x57e
> +			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1
> 0x57e
> +			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2
> 0x57e
> +			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3
> 0x57e
> +			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC
> 0x5fe
> +			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL
> 0x57e
> +		>;
> +	};
> +
> +	pinctrl_lpi2c2: lpi2c2grp {
> +		fsl,pins =3D <
> +			MX93_PAD_I2C2_SCL__LPI2C2_SCL
> 	0x40000b9e
> +			MX93_PAD_I2C2_SDA__LPI2C2_SDA
> 	0x40000b9e
> +		>;
> +	};
> +
> +	pinctrl_usdhc1: usdhc1grp {
> +		fsl,pins =3D <
> +			MX93_PAD_SD1_CLK__USDHC1_CLK
> 	0x15fe
> +			MX93_PAD_SD1_CMD__USDHC1_CMD
> 	0x13fe
> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0
> 	0x13fe
> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1
> 	0x13fe
> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2
> 	0x13fe
> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3
> 	0x13fe
> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4
> 	0x13fe
> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5
> 	0x13fe
> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6
> 	0x13fe
> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7
> 	0x13fe
> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE
> 	0x15fe
> +		>;
> +	};
> +
> +	pinctrl_usdhc2: usdhc2grp {
> +		fsl,pins =3D <
> +			MX93_PAD_SD2_CLK__USDHC2_CLK
> 	0x170e
> +			MX93_PAD_SD2_CMD__USDHC2_CMD
> 	0x130e
> +			MX93_PAD_SD2_DATA0__USDHC2_DATA0
> 	0x130e
> +			MX93_PAD_SD2_DATA1__USDHC2_DATA1
> 0x130e
> +			MX93_PAD_SD2_DATA2__USDHC2_DATA2
> 0x130e
> +			MX93_PAD_SD2_DATA3__USDHC2_DATA3
> 0x130e
> +			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT
> 	0x51e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +		fsl,pins =3D <
> +			MX93_PAD_SD2_CD_B__GPIO3_IO00
> 	0x31e
> +		>;
> +	};
> +};
> --
> 2.34.1
>=20