Received-SPF: pass (google.com: domain of linux-kernel+bounces-156794-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Precedence: bulk
MIME-Version: 1.0
References: <20240424101503.635364-1-quic_tengfan@quicinc.com> <20240424101503.635364-4-quic_tengfan@quicinc.com>
In-Reply-To: <20240424101503.635364-4-quic_tengfan@quicinc.com>
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Wed, 24 Apr 2024 14:23:21 +0300
Message-ID: <CAA8EJpqiXqsNq0B6EHnqubPcUzwJ0bc0y3rJ4RfrRimKifPf0Q@mail.gmail.com>
Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm4450: Supply clock from cpufreq
 node to CPUs
To: Tengfei Fan <quic_tengfan@quicinc.com>
Cc: rafael@kernel.org, viresh.kumar@linaro.org, robh@kernel.org, 
	krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, 
	konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, 
	linux-pm@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"

On Wed, 24 Apr 2024 at 13:17, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>
> Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply
> clocks to the CPU cores. But this relationship is not represented in DTS
> so far.
>
> So let's make cpufreq node as the clock provider and CPU nodes as the
> consumers. The clock index for each CPU node is based on the frequency
> domain index.

Is there any reason why this is not a part of the previous patch?

>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm4450.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> index 92badfd5b0e1..8d75c4f9731c 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> @@ -47,6 +47,7 @@ CPU0: cpu@0 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a55";
>                         reg = <0x0 0x0>;
> +                       clocks = <&cpufreq_hw 0>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_0>;
>                         power-domains = <&CPU_PD0>;
> @@ -72,6 +73,7 @@ CPU1: cpu@100 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a55";
>                         reg = <0x0 0x100>;
> +                       clocks = <&cpufreq_hw 0>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_100>;
>                         power-domains = <&CPU_PD0>;
> @@ -91,6 +93,7 @@ CPU2: cpu@200 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a55";
>                         reg = <0x0 0x200>;
> +                       clocks = <&cpufreq_hw 0>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_200>;
>                         power-domains = <&CPU_PD0>;
> @@ -110,6 +113,7 @@ CPU3: cpu@300 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a55";
>                         reg = <0x0 0x300>;
> +                       clocks = <&cpufreq_hw 0>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_300>;
>                         power-domains = <&CPU_PD0>;
> @@ -129,6 +133,7 @@ CPU4: cpu@400 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a55";
>                         reg = <0x0 0x400>;
> +                       clocks = <&cpufreq_hw 0>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_400>;
>                         power-domains = <&CPU_PD0>;
> @@ -148,6 +153,7 @@ CPU5: cpu@500 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a55";
>                         reg = <0x0 0x500>;
> +                       clocks = <&cpufreq_hw 0>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_500>;
>                         power-domains = <&CPU_PD0>;
> @@ -167,6 +173,7 @@ CPU6: cpu@600 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a78";
>                         reg = <0x0 0x600>;
> +                       clocks = <&cpufreq_hw 1>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_600>;
>                         power-domains = <&CPU_PD0>;
> @@ -186,6 +193,7 @@ CPU7: cpu@700 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a78";
>                         reg = <0x0 0x700>;
> +                       clocks = <&cpufreq_hw 1>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_700>;
>                         power-domains = <&CPU_PD0>;
> --
> 2.25.1
>
>


-- 
With best wishes
Dmitry