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 <20240401-typec-fix-sm8250-v3-8-604dce3ad103@linaro.org> <d57ab72d-2604-4115-9973-1ce0f24b159f@linaro.org>
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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Wed, 24 Apr 2024 15:46:39 +0300
Message-ID: <CAA8EJprdLB3+30wvVZjpC5pWKUzgw+Mg54YkN3SvU-Ovc25Qpg@mail.gmail.com>
Subject: Re: [PATCH v3 8/9] arm64: dts: qcom: x1e80100: describe USB signals properly
To: Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	"Bryan O'Donoghue" <bryan.odonoghue@linaro.org>, linux-arm-msm@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	Luca Weiss <luca.weiss@fairphone.com>
Content-Type: text/plain; charset="UTF-8"

On Tue, 2 Apr 2024 at 17:41, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 1.04.2024 10:33 PM, Dmitry Baryshkov wrote:
> > Follow example of other platforms. Rename HS graph nodes to contain
> > 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 149 +++++++++++++++++++++++++++++++--
> >  1 file changed, 141 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index f5a3b39ae70e..3213eccc3a3a 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > @@ -2543,6 +2543,33 @@ usb_1_ss0_qmpphy: phy@fd5000 {
> >                       #phy-cells = <1>;
> >
> >                       status = "disabled";
> > +
> > +                     ports {
> > +                             #address-cells = <1>;
> > +                             #size-cells = <0>;
> > +
> > +                             port@0 {
> > +                                     reg = <0>;
> > +
> > +                                     usb_1_ss0_qmpphy_out: endpoint {
> > +                                     };
> > +                             };
> > +
> > +                             port@1 {
> > +                                     reg = <1>;
> > +
> > +                                     usb_1_ss0_qmpphy_usb_ss_in: endpoint {
> > +                                             remote-endpoint = <&usb_1_ss0_dwc3_ss>;
> > +                                     };
> > +                             };
> > +
> > +                             port@2 {
> > +                                     reg = <2>;
> > +
> > +                                     usb_1_ss0_qmpphy_dp_in: endpoint {
>
> This is more than just DP AFAIU, please call it SBU

This is not the SBU lane. This is for the SS signals. We are not fully
modelling the SBU signals yet anyway.

-- 
With best wishes
Dmitry