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From: Niko Pasaloukos <nikolaos.pasaloukos@blaize.com>
To: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>
CC: Niko Pasaloukos <nikolaos.pasaloukos@blaize.com>,
        James Cowgill
	<james.cowgill@blaize.com>,
        Matt Redfearn <matthew.redfearn@blaize.com>,
        Neil
 Jones <neil.jones@blaize.com>, Arnd Bergmann <arnd@arndb.de>,
        Olof Johansson
	<olof@lixom.net>, "soc@kernel.org" <soc@kernel.org>,
        Rob Herring
	<robh@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        "devicetree@vger.kernel.org"
	<devicetree@vger.kernel.org>
Subject: [PATCH v2 6/7] arm64: Add initial support for Blaize BLZP1600 CB2
Thread-Topic: [PATCH v2 6/7] arm64: Add initial support for Blaize BLZP1600
 CB2
Thread-Index: AQHalkv6j7L/VUx8ekGpZfmYzieIYw==
Date: Wed, 24 Apr 2024 13:33:23 +0000
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Adds support for the Blaize CB2 development board based on
BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.

The blaize-blzp1600.dtsi is the common part for the SoC,
blaize-blzp1600-som.dtsi is the common part for the SoM and
blaize-blzp1600-cb2.dts is the board specific file.

'make dtbs_check' complains about ['ti,ina3221'] and ['national,lm96163']
which are already upstreamed drivers with no yaml documentation.

Co-developed-by: James Cowgill <james.cowgill@blaize.com>
Signed-off-by: James Cowgill <james.cowgill@blaize.com>
Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com>
Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com>
Co-developed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/blaize/Makefile           |   2 +
 .../boot/dts/blaize/blaize-blzp1600-cb2.dts   |  84 +++++++
 .../boot/dts/blaize/blaize-blzp1600-som.dtsi  |  23 ++
 .../boot/dts/blaize/blaize-blzp1600.dtsi      | 211 ++++++++++++++++++
 5 files changed, 321 insertions(+)
 create mode 100644 arch/arm64/boot/dts/blaize/Makefile
 create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
 create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
 create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 30dd6347a929..601b6381ea0c 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y +=3D apm
 subdir-y +=3D apple
 subdir-y +=3D arm
 subdir-y +=3D bitmain
+subdir-y +=3D blaize
 subdir-y +=3D broadcom
 subdir-y +=3D cavium
 subdir-y +=3D exynos
diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blai=
ze/Makefile
new file mode 100644
index 000000000000..595e7a350300
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) +=3D blaize-blzp1600-cb2.dtb
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm6=
4/boot/dts/blaize/blaize-blzp1600-cb2.dts
new file mode 100644
index 000000000000..0bdec7e81380
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "blaize-blzp1600-som.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	model =3D "Blaize BLZP1600 SoM1600P CB2 Development Board";
+
+	compatible =3D "blaize,blzp1600-cb2", "blaize,blzp1600";
+
+	aliases {
+		serial0 =3D &uart0;
+	};
+
+	chosen {
+		stdout-path =3D "serial0:115200";
+	};
+};
+
+&i2c0 {
+	clock-frequency =3D <100000>;
+	status =3D "okay";
+};
+
+&i2c1 {
+	clock-frequency =3D <100000>;
+	status =3D "okay";
+};
+
+&i2c3 {
+	clock-frequency =3D <100000>;
+	status =3D "okay";
+
+	gpio_expander: gpio@74 {
+		compatible =3D "ti,tca9539";
+		reg =3D <0x74>;
+		gpio-controller;
+		#gpio-cells =3D <2>;
+		gpio-line-names =3D "RSP_PIN_7",	/* GPIO_0 */
+				  "RSP_PIN_11",	/* GPIO_1 */
+				  "RSP_PIN_13",	/* GPIO_2 */
+				  "RSP_PIN_15",	/* GPIO_3 */
+				  "RSP_PIN_27",	/* GPIO_4 */
+				  "RSP_PIN_29",	/* GPIO_5 */
+				  "RSP_PIN_31",	/* GPIO_6 */
+				  "RSP_PIN_33",	/* GPIO_7 */
+				  "RSP_PIN_37",	/* GPIO_8 */
+				  "RSP_PIN_16",	/* GPIO_9 */
+				  "RSP_PIN_18",	/* GPIO_10 */
+				  "RSP_PIN_22",	/* GPIO_11 */
+				  "RSP_PIN_28",	/* GPIO_12 */
+				  "RSP_PIN_32",	/* GPIO_13 */
+				  "RSP_PIN_36",	/* GPIO_14 */
+				  "TP31";	/* GPIO_15 */
+	};
+
+	gpio_expander_m2: gpio@75 {
+		compatible =3D "ti,tca9539";
+		reg =3D <0x75>;
+		gpio-controller;
+		#gpio-cells =3D <2>;
+		gpio-line-names =3D "M2_W_DIS1_N",	/* GPIO_0 */
+				  "M2_W_DIS2_N",	/* GPIO_1 */
+				  "M2_UART_WAKE_N",	/* GPIO_2 */
+				  "M2_COEX3",		/* GPIO_3 */
+				  "M2_COEX_RXD",	/* GPIO_4 */
+				  "M2_COEX_TXD",	/* GPIO_5 */
+				  "M2_VENDOR_PIN40",	/* GPIO_6 */
+				  "M2_VENDOR_PIN42",	/* GPIO_7 */
+				  "M2_VENDOR_PIN38",	/* GPIO_8 */
+				  "M2_SDIO_RST_N",	/* GPIO_9 */
+				  "M2_SDIO_WAKE_N",	/* GPIO_10 */
+				  "M2_PETN1",		/* GPIO_11 */
+				  "M2_PERP1",		/* GPIO_12 */
+				  "M2_PERN1",		/* GPIO_13 */
+				  "UIM_SWP",		/* GPIO_14 */
+				  "UART1_TO_RSP";	/* GPIO_15 */
+	};
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm=
64/boot/dts/blaize/blaize-blzp1600-som.dtsi
new file mode 100644
index 000000000000..efac0d6b3d60
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include "blaize-blzp1600.dtsi"
+
+/ {
+	memory@1000 {
+		device_type =3D "memory";
+		reg =3D <0x0 0x00001000 0xfffff000>;
+	};
+};
+
+/* i2c4 bus is available only on the SoM, not on the board */
+&i2c4 {
+	clock-frequency =3D <100000>;
+	status =3D "okay";
+};
+
+&uart0 {
+	status =3D "okay";
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/b=
oot/dts/blaize/blaize-blzp1600.dtsi
new file mode 100644
index 000000000000..ad1e502559d8
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/blaize,blzp1600-reset.h>
+#include <dt-bindings/clock/blaize,blzp1600-clk.h>
+
+/ {
+	interrupt-parent =3D <&gic>;
+	#address-cells =3D <2>;
+	#size-cells =3D <1>;
+
+	cpus {
+		#address-cells =3D <2>;
+		#size-cells =3D <0>;
+
+		cpu0: cpu@0 {
+			compatible =3D "arm,cortex-a53";
+			device_type =3D "cpu";
+			enable-method =3D "psci";
+			reg =3D <0x0 0x0>;
+			next-level-cache =3D <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			compatible =3D "arm,cortex-a53";
+			device_type =3D "cpu";
+			enable-method =3D "psci";
+			reg =3D <0x0 0x1>;
+			next-level-cache =3D <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible =3D "cache";
+			cache-level =3D <2>;
+			cache-unified;
+		};
+	};
+
+	timer {
+		compatible =3D "arm,armv8-timer";
+		interrupts =3D /* Physical Secure PPI */
+			     <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Physical Non-Secure PPI */
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Hypervisor PPI */
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Virtual PPI */
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	psci {
+		compatible =3D "arm,psci-1.0", "arm,psci-0.2";
+		method =3D "smc";
+	};
+
+	pmu {
+		compatible =3D "arm,cortex-a53-pmu";
+		interrupts =3D <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity =3D <&cpu0>, <&cpu1>;
+	};
+
+	sram@0 {
+		/*
+		 * On BLZP1600 there is no general purpose (non-secure) SRAM.
+		 * A small DDR memory space has been reserved for general use.
+		 */
+		compatible =3D "mmio-sram";
+		reg =3D <0x0 0x00000000 0x00001000>;
+		#address-cells =3D <1>;
+		#size-cells =3D <1>;
+		ranges =3D <0 0x0 0x00000000 0x1000>;
+
+		/* SCMI reserved buffer space on DDR space */
+		scmi0_shm: scmi-sram@800 {
+			compatible =3D "arm,scmi-shmem";
+			reg =3D <0x800 0x80>;
+		};
+	};
+
+	firmware {
+		scmi {
+			compatible =3D "arm,scmi-smc";
+			arm,smc-id =3D <0x82002000>;
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+
+			shmem =3D <&scmi0_shm>;
+
+			scmi_clk: protocol@14 {
+				reg =3D <0x14>;
+				#clock-cells =3D <1>;
+			};
+
+			scmi_rst: protocol@16 {
+				reg =3D <0x16>;
+				#reset-cells =3D <1>;
+			};
+		};
+	};
+
+	soc {
+		compatible =3D "simple-bus";
+		#address-cells =3D <2>;
+		#size-cells =3D <1>;
+		ranges;
+
+		gic: interrupt-controller@200410000 {
+			compatible =3D "arm,gic-400";
+			#interrupt-cells =3D <3>;
+			#address-cells =3D <0>;
+			interrupt-controller;
+			reg =3D <0x2 0x00410000 0x20000>,
+			      <0x2 0x00420000 0x20000>,
+			      <0x2 0x00440000 0x20000>,
+			      <0x2 0x00460000 0x20000>;
+			interrupts =3D <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
+						 IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		uart0: serial@2004d0000 {
+			compatible =3D "ns16550a";
+			reg =3D <0x2 0x004d0000 0x1000>;
+			clocks =3D <&scmi_clk BLZP1600_UART0_CLK>;
+			resets =3D <&scmi_rst BLZP1600_UART0_RST>;
+			reg-shift =3D <2>;
+			interrupts =3D <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			status =3D "disabled";
+		};
+
+		uart1: serial@2004e0000 {
+			compatible =3D "ns16550a";
+			reg =3D <0x2 0x004e0000 0x1000>;
+			clocks =3D <&scmi_clk BLZP1600_UART1_CLK>;
+			resets =3D <&scmi_rst BLZP1600_UART1_RST>;
+			reg-shift =3D <2>;
+			interrupts =3D <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			status =3D "disabled";
+		};
+
+		i2c0: i2c@2004f0000 {
+			compatible =3D "snps,designware-i2c";
+			reg =3D <0x2 0x004f0000 0x1000>;
+			interrupts =3D <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks =3D <&scmi_clk BLZP1600_I2C0_CLK>;
+			resets =3D <&scmi_rst BLZP1600_I2C0_RST>;
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+			status =3D "disabled";
+		};
+
+		i2c1: i2c@200500000 {
+			compatible =3D "snps,designware-i2c";
+			reg =3D <0x2 0x00500000 0x1000>;
+			interrupts =3D <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks =3D <&scmi_clk BLZP1600_I2C1_CLK>;
+			resets =3D <&scmi_rst BLZP1600_I2C1_RST>;
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+			status =3D "disabled";
+		};
+
+		i2c2: i2c@200510000 {
+			compatible =3D "snps,designware-i2c";
+			reg =3D <0x2 0x00510000 0x1000>;
+			interrupts =3D <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks =3D <&scmi_clk BLZP1600_I2C2_CLK>;
+			resets =3D <&scmi_rst BLZP1600_I2C2_RST>;
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+			status =3D "disabled";
+		};
+
+		i2c3: i2c@200520000 {
+			compatible =3D "snps,designware-i2c";
+			reg =3D <0x2 0x00520000 0x1000>;
+			interrupts =3D <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks =3D <&scmi_clk BLZP1600_I2C3_CLK>;
+			resets =3D <&scmi_rst BLZP1600_I2C3_RST>;
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+			status =3D "disabled";
+		};
+
+		i2c4: i2c@200530000 {
+			compatible =3D "snps,designware-i2c";
+			reg =3D <0x2 0x00530000 0x1000>;
+			interrupts =3D <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks =3D <&scmi_clk BLZP1600_I2C4_CLK>;
+			resets =3D <&scmi_rst BLZP1600_I2C4_RST>;
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+			status =3D "disabled";
+		};
+
+		arm_cc712: crypto@200550000 {
+			compatible =3D "arm,cryptocell-712-ree";
+			reg =3D <0x2 0x00550000 0x1000>;
+			interrupts =3D <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks =3D <&scmi_clk 7>;
+		};
+	};
+};
--=20
2.34.1