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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Date: Wed, 24 Apr 2024 07:44:16 -0700
Message-ID: <CAJM55Z_G5EKSjHztCQ+gXDGwfpziZTE=HsHmwydJWB-uorMOqA@mail.gmail.com>
Subject: RE: [PATCH v3 1/2] cache: Add StarFive StarLink cache management for
 StarFive JH8100
To: Joshua Yeong <joshua.yeong@starfivetech.com>, 
	Emil Renner Berthing <emil.renner.berthing@canonical.com>, "robh@kernel.org" <robh@kernel.org>, 
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>, "conor+dt@kernel.org" <conor+dt@kernel.org>, 
	"conor@kernel.org" <conor@kernel.org>, "paul.walmsley@sifive.com" <paul.walmsley@sifive.com>, 
	"palmer@dabbelt.com" <palmer@dabbelt.com>, "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>, 
	Leyfoon Tan <leyfoon.tan@starfivetech.com>, JeeHeng Sia <jeeheng.sia@starfivetech.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, 
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, 
	"linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>
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Joshua Yeong wrote:
>
>
> Emil Renner Berthing wrote:
> > Joshua Yeong wrote:
> > > Emil Renner Berthing wrote:
> > > > Joshua Yeong wrote:
> > > > > Add StarFive Starlink cache management driver for
> > > > > JH8100 SoC. This driver enables RISC-V non-standard cache
> > > > > operation on
> > > > > JH8100 that does not support Zicbom extension instructions.
> > > > >
> > > > > Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
> > > > > ---
> > > > >  drivers/cache/Kconfig                   |   9 ++
> > > > >  drivers/cache/Makefile                  |   5 +-
> > > > >  drivers/cache/starfive_starlink_cache.c | 135
> > > > > ++++++++++++++++++++++++
> > > > >  3 files changed, 147 insertions(+), 2 deletions(-)  create mode
> > > > > 100644 drivers/cache/starfive_starlink_cache.c
> > > > >
> > > > > diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index
> > > > > 9345ce4976d7..9181cd391f53 100644
> > > > > --- a/drivers/cache/Kconfig
> > > > > +++ b/drivers/cache/Kconfig
> > > > > @@ -14,4 +14,13 @@ config SIFIVE_CCACHE
> > > > >  	help
> > > > >  	  Support for the composable cache controller on SiFive platfor=
ms.
> > > > >
> > > > > +config STARFIVE_STARLINK_CACHE
> > > > > +	bool "StarFive StarLink Cache controller"
> > > > > +	depends on RISCV
> > > > > +	depends on ARCH_STARFIVE
> > > > > +	select RISCV_DMA_NONCOHERENT
> > > > > +	select RISCV_NONSTANDARD_CACHE_OPS
> > > > > +	help
> > > > > +	  Support for the StarLink cache controller on StarFive platfor=
ms.
> > > >
> > > > This is a bit misleading. The JH71x0s don't have this. It's only on
> > > > the JH8100 so far, and hopefully later SoCs will just implement RIS=
C-V
> > standards for this.
> > > > So maybe something like
> > > >
> > > > "Support for the StarLink cache controller on the StarFive JH8100 S=
oC."
> > > >
> > >
> > > Hi Emil,
> > >
> > > The StarLink-500 cache controller is not designed exclusively for JH8=
100 SoC.
> > > While it is true that it currently exists on the StarFive platform,
> > > CPU/SoC that does not come with Zicbom extensions supported would nee=
d
> > > to rely on this cache drive to do cache management operations. I thin=
k
> > > we don=E2=80=99t need to mentioned 'JH8100 SoC' here.
> >
> > Wait, in the previous mail you said that future designs will implement =
Zicbom
> > and not need this work-around, but here you're talking about other SoCs=
 that
> > do need it. So which is it?
>
> If you visit the company website and look for StarLink-500, you will find=
 that
> it is a standalone IP that the company is selling as an interconnect. Any=
one
> who integrates StarLink without Zicbom extensions may utilize the cache
> management operation from this IP.

So then the "on StarFive platforms" part is wrong? Or will this always go
together with the Dubhe cores?

>
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