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24 Apr 2024 08:30:18 -0700 Received: from [10.212.107.188] (kliang2-mobl1.ccr.corp.intel.com [10.212.107.188]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by linux.intel.com (Postfix) with ESMTPS id 422D8206D89D; Wed, 24 Apr 2024 08:30:16 -0700 (PDT) Message-ID: <7f1014fc-eb0a-4989-8efa-245d5b6937cd@linux.intel.com> Date: Wed, 24 Apr 2024 11:30:14 -0400 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 13/16] perf parse-events: Improvements to modifier parsing To: Ian Rogers Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , James Clark , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , linux-riscv@lists.infradead.org, Beeman Strong References: <20240416061533.921723-1-irogers@google.com> <20240416061533.921723-14-irogers@google.com> <7df3ff63-a421-42cc-bcaa-b0254ff6a0e8@linux.intel.com> Content-Language: en-US From: "Liang, Kan" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 2024-04-24 11:18 a.m., Ian Rogers wrote: > On Fri, Apr 19, 2024 at 6:20 AM Liang, Kan wrote: >> >> >> >> On 2024-04-19 2:22 a.m., Ian Rogers wrote: >>>>> + /* Simple modifiers copied to the evsel. */ >>>>> + if (mod.precise) { >>>>> + u8 precise = evsel->core.attr.precise_ip + mod.precise; >>>>> + /* >>>>> + * precise ip: >>>>> + * >>>>> + * 0 - SAMPLE_IP can have arbitrary skid >>>>> + * 1 - SAMPLE_IP must have constant skid >>>>> + * 2 - SAMPLE_IP requested to have 0 skid >>>>> + * 3 - SAMPLE_IP must have 0 skid >>>>> + * >>>>> + * See also PERF_RECORD_MISC_EXACT_IP >>>>> + */ >>>>> + if (precise > 3) { >>>> The pmu_max_precise() should return the max precise the current kernel >>>> supports. It checks the /sys/devices/cpu/caps/max_precise. >>>> >>>> I think we should use that value rather than hard code it to 3. >>> I'll add an extra patch to do that. I'm a bit concerned it may break >>> event parsing on platforms not supporting max_precise of 3. >> >> The kernel already rejects the precise_ip > max_precise (using the same >> x86_pmu_max_precise()). It should be fine to apply the same logic in the >> tool. >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/events/core.c#n566 >> >> Will the extra patch be sent separately? > > Let's do it separately. I'm concerned about the behavior on AMD (and > possibly similar architectures) where certain events support precision > like cycles, as they detour to the IBS PMU, but not all events support > it. The max_precise should reflect that AMD's Zen core PMU does > support precision as a consequence of detouring to IBS, but maybe > things in sysfs aren't set up correctly. > The x86_pmu_max_precise() is a generic function for X86. It should apply to AMD as well. A separate patch looks good to me. Thanks, Kan