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Wed, 24 Apr 2024 08:13:42 -0700 (PDT) Date: Wed, 24 Apr 2024 11:13:40 -0400 From: Charlie Jenkins To: Conor Dooley Cc: Alexandre Ghiti , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v3 06/17] riscv: Fix extension subset checking Message-ID: References: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com> <20240420-dev-charlie-support_thead_vector_6_9-v3-6-67cff4271d1d@rivosinc.com> <6c624361-a968-498b-a9fb-ea2aaec70ce8@ghiti.fr> <20240424-wildly-goofy-c81aac6f8cd7@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240424-wildly-goofy-c81aac6f8cd7@spud> On Wed, Apr 24, 2024 at 03:51:54PM +0100, Conor Dooley wrote: > On Wed, Apr 24, 2024 at 04:22:02PM +0200, Alexandre Ghiti wrote: > > Hi Charlie, > > > > On 21/04/2024 03:04, Charlie Jenkins wrote: > > > This loop is supposed to check if ext->subset_ext_ids[j] is valid, rather > > > than if ext->subset_ext_ids[i] is valid, before setting the extension > > > id ext->subset_ext_ids[j] in isainfo->isa. > > > > > > Signed-off-by: Charlie Jenkins > > > Reviewed-by: Conor Dooley > > > Fixes: 0d8295ed975b ("riscv: add ISA extension parsing for scalar crypto") > > > --- > > > arch/riscv/kernel/cpufeature.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > > index 48874aac4871..b537731cadef 100644 > > > --- a/arch/riscv/kernel/cpufeature.c > > > +++ b/arch/riscv/kernel/cpufeature.c > > > @@ -609,7 +609,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) > > > if (ext->subset_ext_size) { > > > for (int j = 0; j < ext->subset_ext_size; j++) { > > > - if (riscv_isa_extension_check(ext->subset_ext_ids[i])) > > > + if (riscv_isa_extension_check(ext->subset_ext_ids[j])) > > > set_bit(ext->subset_ext_ids[j], isainfo->isa); > > > } > > > } > > > > > > > I think this should go into -fixes, let's check with Palmer if he wants to > > take this patch only or if you should send the patch on its own. > > I think splitting out this and patch 1 into a new series targeting fixes > would probably make things clearer? Okay I can do that. I will give it a bit more time before I send this series split into two to allow time for the rest of the patches to gather comments so I avoid sending too many duplicate patches. - Charlie