Received-SPF: pass (google.com: domain of linux-kernel+bounces-157425-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1;
From: =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
To: "Rafael J. Wysocki" <rafael@kernel.org>, Sunil V L
 <sunilvl@ventanamicro.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
 linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev, Catalin Marinas
 <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Paul Walmsley
 <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou
 <aou@eecs.berkeley.edu>, "Rafael J . Wysocki" <rafael@kernel.org>, Len
 Brown <lenb@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Anup Patel
 <anup@brainfault.org>, Thomas Gleixner <tglx@linutronix.de>, Samuel
 Holland <samuel.holland@sifive.com>, Robert Moore
 <robert.moore@intel.com>, Haibo1 Xu <haibo1.xu@intel.com>, Conor Dooley
 <conor.dooley@microchip.com>, Andrew Jones <ajones@ventanamicro.com>,
 Atish Kumar Patra <atishp@rivosinc.com>, Andrei Warkentin
 <andrei.warkentin@intel.com>, Marc Zyngier <maz@kernel.org>
Subject: Re: [RFC PATCH v4 00/20] RISC-V: ACPI: Add external interrupt
 controller support
In-Reply-To: <CAJZ5v0gTzn3TDoh0+0UQjMeJVdU+z16dDOT_fKMhr0XrOxyRtA@mail.gmail.com>
References: <20240415170113.662318-1-sunilvl@ventanamicro.com>
 <CAJZ5v0gTzn3TDoh0+0UQjMeJVdU+z16dDOT_fKMhr0XrOxyRtA@mail.gmail.com>
Date: Wed, 24 Apr 2024 19:55:50 +0200
Message-ID: <871q6uir15.fsf@all.your.base.are.belong.to.us>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: quoted-printable

"Rafael J. Wysocki" <rafael@kernel.org> writes:

> On Mon, Apr 15, 2024 at 7:01=E2=80=AFPM Sunil V L <sunilvl@ventanamicro.c=
om> wrote:
>>
>> This series adds support for the below ECR approved by ASWG.
>> 1) MADT - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia=
7zR/view?usp=3Dsharing
>>
>> The series primarily enables irqchip drivers for RISC-V ACPI based
>> platforms.
>>
>> The series can be broadly categorized like below.
>>
>> 1) PCI ACPI related functions are migrated from arm64 to common file so
>> that we don't need to duplicate them for RISC-V.
>>
>> 2) Added support for re-ordering the probe of interrupt controllers when
>> IRQCHIP_ACPI_DECLARE is used.
>>
>> 3) To ensure probe order between interrupt controllers and devices,
>> implicit dependency is created similar to when _DEP is present.
>>
>> 4) When PNP devices like Generic 16550A UART, have the dependency on the
>> interrupt controller, they will not be added to PNP data structures. So,
>> added second phase of pnpacpi_init to handle this.
>>
>> 5) ACPI support added in RISC-V interrupt controller drivers.
>>
>> This series is still kept as RFC to seek feedback on above design
>> changes. Looking forward for the feedback!
>
> I've looked at the patches and I don't see anything deeply concerning
> in them from the ACPI core code perspective.
>
> The changes look reasonably straightforward to me.

Sunil, given Rafael's input, it sounds like it's time for a patch
proper. This is really the missing piece to make ACPI usable on RISC-V!

Thanks for the nice work!
Bj=C3=B6rn

FWIW,
Tested-by: Bj=C3=B6rn T=C3=B6pel <bjorn@rivosinc.com>