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AJvYcCVSqjs0UHk2AOLwNDIRwb+LMbKv3uvt25pldNcRLnbi+Xz5rKO75+WdORX0/eeBOKtUnxkHp2Eby1hakPm3+aXAcV1+qU7hQvQAPKc5 X-Gm-Message-State: AOJu0YxBKWqL/g71lO8hIAk3Z5PlI+7/km1PCIPxSBqxSbheRGwhNuEb pOq49cyBwNA/gVainYFJtBe0CBs/8mziYw4Zr495pR5arhogsimrdVXifK7nBgB3oEEmAehHr/b hP26P52PU15cJEcsgnat0lkhshC1+oh+fTkt5Ww== X-Received: by 2002:a25:664a:0:b0:de0:d3af:f52f with SMTP id z10-20020a25664a000000b00de0d3aff52fmr4141531ybm.49.1714002451985; Wed, 24 Apr 2024 16:47:31 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240424024508.3857602-1-quic_tengfan@quicinc.com> <20240424024508.3857602-4-quic_tengfan@quicinc.com> In-Reply-To: <20240424024508.3857602-4-quic_tengfan@quicinc.com> From: Dmitry Baryshkov Date: Thu, 25 Apr 2024 02:47:21 +0300 Message-ID: Subject: Re: [PATCH v7 3/4] arm64: dts: qcom: add base AIM300 dtsi To: Tengfei Fan Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, kernel@quicinc.com, Fenglin Wu Content-Type: text/plain; charset="UTF-8" On Wed, 24 Apr 2024 at 05:46, Tengfei Fan wrote: > > AIM300 Series is a highly optimized family of modules designed to > support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC > chip etc. > Here is a diagram of AIM300 SoM: > +----------------------------------------+ > |AIM300 SoM | > | | > | +-----+ | > | |--->| UFS | | > | | +-----+ | > | | | > | | | > 3.7v | +-----------------+ | +---------+ | > ---------->| PMIC |----->| QCS8550 | | > | +-----------------+ +---------+ | > | | | > | | | > | | +-----+ | > | |--->| ... | | > | +-----+ | > | | > +----------------------------------------+ > > Co-developed-by: Fenglin Wu > Signed-off-by: Fenglin Wu > Signed-off-by: Tengfei Fan > --- > arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 403 +++++++++++++++++++ > 1 file changed, 403 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi > + > +&pcie_1_phy_aux_clk { > + clock-frequency = <1000>; > +}; Please rebase on top of https://lore.kernel.org/linux-arm-msm/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-0-868b15a17a45@linaro.org/ > + > +&pcie1 { > + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; Please add pinctrl configurations for pcie0 and pcie1 With that fixed: Reviewed-by: Dmitry Baryshkov > +}; > + > -- With best wishes Dmitry