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Thu, 25 Apr 2024 00:12:42 +0000 Received: from SJ1PR11MB6083.namprd11.prod.outlook.com ([fe80::fca9:7c00:b6d0:1d62]) by SJ1PR11MB6083.namprd11.prod.outlook.com ([fe80::fca9:7c00:b6d0:1d62%5]) with mapi id 15.20.7519.015; Thu, 25 Apr 2024 00:12:42 +0000 From: "Luck, Tony" To: Mark Brown CC: Borislav Petkov , Jaroslav Kysela , "Takashi Iwai" , "Rojewski, Cezary" , Pierre-Louis Bossart , Liam Girdwood , Peter Ujfalusi , Bard Liao , Ranjani Sridharan , Kai Vehmanen , =?iso-8859-2?Q?Amadeusz_S=B3awi=F1ski?= , Krzysztof Kozlowski , Kuninori Morimoto , "alsa-devel@alsa-project.org" , "linux-sound@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "patches@lists.linux.dev" Subject: RE: [PATCH v4 68/71] ASoC: Intel: avs: es8336: Switch to new Intel CPU model defines Thread-Topic: [PATCH v4 68/71] ASoC: Intel: avs: es8336: Switch to new Intel CPU model defines Thread-Index: AQHalnNypAm37i9ZEk6+7LiAmvGSwbF4GbEAgAABFJA= Date: Thu, 25 Apr 2024 00:12:41 +0000 Message-ID: References: <20240424181245.41141-1-tony.luck@intel.com> <20240424181550.42466-1-tony.luck@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SJ1PR11MB6083.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 64b094fc-0c61-426f-a846-08dc64bc6cae X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Apr 2024 00:12:41.9576 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: T+fs+vCQWOiBqW26MpCQ5gtkjIxAhL5j+m2ARe+isKEQRlO5RF4eLlBJKCFIpbRIvre3P7htO5bp3PyMfCdvCA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB7849 X-OriginatorOrg: intel.com >> New CPU #defines encode vendor and family as well as model. > > This appears to be part of a series but I've no cover letter or anything > else from it. What's the story for dependencies and merging? Sorry. I should have at least added a link to the individual patches to provide some pointers. It's my first time with a patch bomb of this size, so I'm learning as I go. You can pick up the cover letter, and the whole series, from lore with: $ b4 am 20240424181245.41141-1-tony.luck@intel.com or pull from: git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux.git = new_families_v4 The dependencies for this patch are already in tip x86/cpu, and in linux-ne= xt. Basically these three patches: f055b6260eb3 x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h e6dfdc2e89a0 x86/cpu/vfm: Add new macros to work with (vendor/family/model)= values a9d0adce6907 x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x8= 6 For merging. This can either go through tip with the rest of the series. Or you can take it through your own tree after the dependencies get merged into v6.10-rc1 (I'm expecting this to take a couple of release cycles to complete). -Tony