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a=ed25519-sha256; t=1714016731; l=2745; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=JY3AmVLcwPO1P6DoNmmLgo63YdF0tdPmQSHA95BBAXc=; b=DgZjfTY8hxgg+sMTt8VV8lSZA5iAiK/lYZ/iWzcIWEP81S7lK5zyYOzmW0p0s9OGPOxp8IPYU IuctO/21nrVBNeJH8bFK2L0ENXmW50xJZji0PtUGMaFGx+hauBLoWN9 X-Developer-Key: i=quic_bjorande@quicinc.com; a=ed25519; pk=VkhObtljigy9k0ZUIE1Mvr0Y+E1dgBEH9WoLQnUtbIM= X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 2FbXZ2uIL-MpoqbqOa-QYvGOdC7pKBb0 X-Proofpoint-GUID: 2FbXZ2uIL-MpoqbqOa-QYvGOdC7pKBb0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-25_02,2024-04-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 adultscore=0 clxscore=1011 priorityscore=1501 phishscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404250025 When a GPIO is configured as OPEN_DRAIN gpiolib will in gpiod_direction_output() attempt to configure the open-drain property of the hardware and if this fails fall back to software emulation of this state. The TLMM block in most Qualcomm platform does not implement such functionality, so this call would be expected to fail. But due to lack of checks for this condition, the zero-initialized od_bit will cause this request to silently corrupt the lowest bit in the config register (which typically is part of the bias configuration) and happily continue on. Fix this by checking if the od_bit value is unspecified and if so fail the request to avoid the unexpected state, and to make sure the software fallback actually kicks in. It is assumed for now that no implementation will come into existence with BIT(0) being the open-drain bit, simply for convenience sake. Fixes: 13355ca35cd1 ("pinctrl: qcom: ipq4019: add open drain support") Signed-off-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-msm.c | 2 ++ drivers/pinctrl/qcom/pinctrl-msm.h | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index aeaf0d1958f5..329474dc21c0 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -313,6 +313,8 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, *mask |= BIT(g->i2c_pull_bit) >> *bit; break; case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!g->od_bit) + return -EOPNOTSUPP; *bit = g->od_bit; *mask = 1; break; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 63852ed70295..7b8cd1832112 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -51,7 +51,8 @@ struct pinctrl_pin_desc; * @mux_bit: Offset in @ctl_reg for the pinmux function selection. * @pull_bit: Offset in @ctl_reg for the bias configuration. * @drv_bit: Offset in @ctl_reg for the drive strength configuration. - * @od_bit: Offset in @ctl_reg for controlling open drain. + * @od_bit: Offset in @ctl_reg for controlling open drain. 0 if + * not supported by target. * @oe_bit: Offset in @ctl_reg for controlling output enable. * @in_bit: Offset in @io_reg for the input bit value. * @out_bit: Offset in @io_reg for the output bit value. --- base-commit: 5e4f84f18c4ee9b0ccdc19e39b7de41df21699dd change-id: 20240424-tlmm-open-drain-8b014c1cfa1a Best regards, -- Bjorn Andersson