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Date: Thu, 25 Apr 2024 09:51:19 +0200
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Subject: Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
To: Thierry Reding <thierry.reding@gmail.com>, Sumit Gupta
 <sumitg@nvidia.com>, robh@kernel.org, conor+dt@kernel.org, maz@kernel.org,
 mark.rutland@arm.com, treding@nvidia.com, jonathanh@nvidia.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
 linux-tegra@vger.kernel.org, amhetre@nvidia.com, bbasu@nvidia.com
References: <20240412130540.28447-1-sumitg@nvidia.com>
 <20240412130540.28447-2-sumitg@nvidia.com>
 <d26f9661-3e50-4a72-9097-fe63a27503f1@linaro.org>
 <D0SHRQVCGJBY.2DPLX9K6VXEYM@gmail.com>
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In-Reply-To: <D0SHRQVCGJBY.2DPLX9K6VXEYM@gmail.com>
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On 24/04/2024 18:26, Thierry Reding wrote:
> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
>> On 12/04/2024 15:05, Sumit Gupta wrote:
>>> MC SID and Broadbast channel register access is restricted for Guest VM.
>>
>> Broadcast
>>
>>> Make both the regions as optional for SoC's from Tegra186 onwards.
>>
>> onward?
>>
>>> Tegra MC driver will skip access to the restricted registers from Guest
>>> if the respective regions are not present in the memory-controller node
>>> of Guest DT.
>>>
>>> Suggested-by: Thierry Reding <treding@nvidia.com>
>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
>>> ---
>>>  .../nvidia,tegra186-mc.yaml                   | 95 ++++++++++---------
>>>  1 file changed, 49 insertions(+), 46 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> index 935d63d181d9..e0bd013ecca3 100644
>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> @@ -34,11 +34,11 @@ properties:
>>>            - nvidia,tegra234-mc
>>>  
>>>    reg:
>>> -    minItems: 6
>>> +    minItems: 4
>>>      maxItems: 18
>>>  
>>>    reg-names:
>>> -    minItems: 6
>>> +    minItems: 4
>>>      maxItems: 18
>>>  
>>>    interrupts:
>>> @@ -151,12 +151,13 @@ allOf:
>>>  
>>>          reg-names:
>>>            items:
>>> -            - const: sid
>>> -            - const: broadcast
>>> -            - const: ch0
>>> -            - const: ch1
>>> -            - const: ch2
>>> -            - const: ch3
>>> +            enum:
>>> +              - sid
>>> +              - broadcast
>>> +              - ch0
>>> +              - ch1
>>> +              - ch2
>>> +              - ch3
>>
>> I understand why sid and broadcast are becoming optional, but why order
>> of the rest is now fully flexible?
> 
> The reason why the order of the rest doesn't matter is because we have
> both reg and reg-names properties and so the order in which they appear
> in the list doesn't matter. The only thing that matters is that the
> entries of the reg and reg-names properties match.

No, that's not true. Client/implementation can pick up by indices and
order always matters, at least as much as possible.

If the reason is "we have reg-names", then the answer is: no. That's not
valid argument. The reason could be that entries are so
fragmented/randomly distributed that order by indices is impossible.

> 
>> This does not even make sid/broadcast optional, but ch0!
> 
> Yeah, this ends up making all entries optional, which isn't what we
> want. I don't know of a way to accurately express this in json-schema,
> though. Do you?

I think oneOf: with two cases. Depends what is exactly optional. The
commit msg is quite poor here. I expect proper rationale and description
of driver. Is sid optional? broadcast? Both? Any? And what does it mean
optional? The address is reserved or address is not existing? Or maybe
address is there, but can be ignored?

> 
> If not, then maybe we need to resort to something like this and also
> mention explicitly in some comment that it is sid and broadcast that are
> optional.
> 
> Thierry

Best regards,
Krzysztof