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Date: Thu, 25 Apr 2024 11:21:25 +0200
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Subject: Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
To: Niko Pasaloukos <nikolaos.pasaloukos@blaize.com>,
 "robh@kernel.org" <robh@kernel.org>,
 "krzysztof.kozlowski+dt@linaro.org" <krzysztof.kozlowski+dt@linaro.org>,
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 "will@kernel.org" <will@kernel.org>, "arnd@arndb.de" <arnd@arndb.de>,
 "olof@lixom.net" <olof@lixom.net>, Neil Jones <neil.jones@blaize.com>,
 Matt Redfearn <matthew.redfearn@blaize.com>,
 James Cowgill <james.cowgill@blaize.com>,
 "heiko.stuebner@cherry.de" <heiko.stuebner@cherry.de>,
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References: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com>
 <20240425091403.17483-5-nikolaos.pasaloukos@blaize.com>
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In-Reply-To: <20240425091403.17483-5-nikolaos.pasaloukos@blaize.com>
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On 25/04/2024 11:15, Niko Pasaloukos wrote:
> Adds support for the Blaize CB2 development board based on
> BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.

Subject: missing dts prefix.


..

> +
> +/ {
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			reg = <0x0 0x0>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			reg = <0x0 0x1>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		l2: l2-cache0 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = /* Physical Secure PPI */
> +			     <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     /* Physical Non-Secure PPI */
> +			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     /* Hypervisor PPI */
> +			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     /* Virtual PPI */
> +			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
> +					  IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0", "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	pmu {

Nodes in top-level look randomly ordered. Any reason why not using DTS
coding style in this regard?

> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>;
> +	};
> +
> +	sram@0 {
> +		/*
> +		 * On BLZP1600 there is no general purpose (non-secure) SRAM.
> +		 * A small DDR memory space has been reserved for general use.
> +		 */
> +		compatible = "mmio-sram";
> +		reg = <0x0 0x00000000 0x00001000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x0 0x00000000 0x1000>;

ranges follow reg

> +
> +		/* SCMI reserved buffer space on DDR space */
> +		scmi0_shm: scmi-sram@800 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x800 0x80>;
> +		};
> +	};
> +
> +	firmware {
> +		scmi {
> +			compatible = "arm,scmi-smc";
> +			arm,smc-id = <0x82002000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			shmem = <&scmi0_shm>;
> +
> +			scmi_clk: protocol@14 {
> +				reg = <0x14>;
> +				#clock-cells = <1>;
> +			};
> +
> +			scmi_rst: protocol@16 {
> +				reg = <0x16>;
> +				#reset-cells = <1>;
> +			};
> +		};
> +	};
> +
> +	soc {

This does not cause dtbs_check W=1 warnings? Surprising a bit... This
should cause big fat warning, so I have doubts patchset was tested.


Best regards,
Krzysztof