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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Thu, 25 Apr 2024 12:37:20 +0100
Message-ID: <CA+V-a8sJTp3EhHHM_26sNdZKVwmOGx35G3hDvb7y33L5+w4JEA@mail.gmail.com>
Subject: Re: [PATCH v3 2/2] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Magnus Damm <magnus.damm@gmail.com>, linux-kernel@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, 
	Biju Das <biju.das.jz@bp.renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Geert,

Thank you for the review.

On Wed, Apr 24, 2024 at 3:59=E2=80=AFPM Geert Uytterhoeven <geert@linux-m68=
k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Apr 22, 2024 at 10:51=E2=80=AFPM Prabhakar <prabhakar.csengg@gmai=
l.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The IX45 block on the RZ/Five SoC has additional mask registers
> > (NMSK/IMSK/TMSK) compared to the RZ/G2L (family) SoC.
> >
> > A new rzfive_irqc_chip irq_chip is introduced for RZ/Five, where functi=
on
> > pointers for irq_(un)mask and irq_(dis/en)able handle the (un)masking
> > of the interrupts. The irq_chip pointer is now passed as an init callba=
ck
> > and stored in the priv pointer to differentiate between RZ/G2L and RZ/F=
ive.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > - Added RZ/Five specific irqchip instead of polluting the functions
> > - Fixed review comments pointed by Biju and Geert
> > - Updated commit message
> > - moved locking respective read/write functions
>
> Thanks for the update!
>
> > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > @@ -138,6 +142,113 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> >         irq_chip_eoi_parent(d);
> >  }
> >
> > +static void rzfive_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *pri=
v,
> > +                                          unsigned int hwirq)
> > +{
> > +       u32 bit =3D BIT(hwirq - IRQC_IRQ_START);
> > +
> > +       raw_spin_lock(&priv->lock);
>
> I think you best move the locking to the callers that really need it...
>
Ok, will do.

> > +       writel_relaxed(readl_relaxed(priv->base + IMSK) | bit, priv->ba=
se + IMSK);
> > +       raw_spin_unlock(&priv->lock);
> > +}
>
> > +static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable)
> > +{
> > +       struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d);
> > +       unsigned int hwirq =3D irqd_to_hwirq(d);
> > +
> > +       if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) {
> > +               u32 offset =3D hwirq - IRQC_TINT_START;
> > +               u32 tssr_offset =3D TSSR_OFFSET(offset);
> > +               u8 tssr_index =3D TSSR_INDEX(offset);
> > +               u32 reg;
> > +
> > +               if (enable)
> > +                       rzfive_irqc_unmask_tint_interrupt(priv, hwirq);
> > +               else
> > +                       rzfive_irqc_mask_tint_interrupt(priv, hwirq);
>
> ... else you will do a lock/unlock here, followed by another one below.
>
and move the above code into the lock below.

Cheers,
Prabhakar