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AJvYcCU9eqGonN2Q9AtpFogWYh9SFSZaaMaQoW9nuSkcNqNCx3Ju7f3qAJd6jwjIW4RwK53cvHC9l8FL0rAccM7AA4Np2NoiH66B5THz8+k8 X-Gm-Message-State: AOJu0YxsZ5G5LaFU8uFoV8ZpJkgmFbFOHsW5clHQ9jjSHFTrffvOSvL6 94FCIr4oSPoEjWf3lZxWdKnKj6YF3cOeo00JC7ud13grrzn/TRlWti4ALVJb7wfMPy8GUrAzOWj tovJta7L3bmIviF12GiLQ4RFutqJTb7OKavpx7A== X-Received: by 2002:a25:fc11:0:b0:de5:5706:b955 with SMTP id v17-20020a25fc11000000b00de55706b955mr243062ybd.4.1714063534487; Thu, 25 Apr 2024 09:45:34 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240422105355.1622177-1-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: From: Ulf Hansson Date: Thu, 25 Apr 2024 18:44:58 +0200 Message-ID: Subject: Re: [PATCH v4 0/8] clk: renesas: rzg2l: Add support for power domains To: Geert Uytterhoeven , Claudiu Cc: mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 24 Apr 2024 at 16:34, Geert Uytterhoeven wro= te: > > Hi Ulf, > > On Mon, Apr 22, 2024 at 12:54=E2=80=AFPM Claudiu wrote: > > From: Claudiu Beznea > > > > Series adds support for power domains on rzg2l driver. > > > > RZ/G2L kind of devices support a functionality called MSTOP (module > > stop/standby). According to hardware manual the module could be switch > > to standby after its clocks are disabled. The reverse order of operatio= n > > should be done when enabling a module (get the module out of standby, > > enable its clocks etc). > > > > In [1] the MSTOP settings were implemented by adding code in driver > > to attach the MSTOP state to the IP clocks. But it has been proposed > > to implement it as power domain. The result is this series. > > > > The DT bindings were updated with power domain IDs (plain integers > > that matches the DT with driver data structures). The current DT > > bindings were updated with module IDs for the modules listed in tables > > with name "Registers for Module Standby Mode" (see HW manual) exception > > being RZ/G3S where, due to the power down functionality, the DDR, > > TZCDDR, OTFDE_DDR were also added. > > > > Domain IDs were added to all SoC specific bindings. > > > > Thank you, > > Claudiu Beznea > > > > Changes in v4: > > - dropped the pwrdn functionality until it is better understanded > > - dropped patch "clk: renesas: rzg2l-cpg: Add suspend/resume > > support for power domains" from v3; this will be replaced > > by propertly calling device_set_wakup_path() in serial console > > driver > > - instantiated the watchdog domain in r8a08g045 clock driver; this > > allow applying r9a08g045 clock patch w/o affecting watchdog and later= , > > after all good with watchdog patches series at [2], only patch > > "arm64: dts: renesas: r9a08g045: Update #power-domain-cells =3D <1>" > > will need to be applied > > Are you happy with this series? I would like to queue patches 1-7 in > renesas-clk for v6.10 (i.e. this week). Yes, the series looks good to me! For the series, feel free to add: Reviewed-by: Ulf Hansson Kind regards Uffe