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From: Adam Ford <aford173@gmail.com>
Date: Thu, 25 Apr 2024 15:30:02 -0500
Message-ID: <CAHCN7xJRgW4Y3YML+tToPw1TgA3o158XCEUcb9p-S+nvDWgzRQ@mail.gmail.com>
Subject: Re: [PATCH V2 2/2] drm/bridge: samsung-dsim: Fix porch calcalcuation rounding
To: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: dri-devel@lists.freedesktop.org, marex@denx.de, aford@beaconembedded.com, 
	Frieder Schrempf <frieder.schrempf@kontron.de>, Inki Dae <inki.dae@samsung.com>, 
	Jagan Teki <jagan@amarulasolutions.com>, Andrzej Hajda <andrzej.hajda@intel.com>, 
	Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <rfoss@kernel.org>, 
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Jonas Karlman <jonas@kwiboo.se>, 
	Jernej Skrabec <jernej.skrabec@gmail.com>, 
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, 
	Thomas Zimmermann <tzimmermann@suse.de>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, 
	Marco Felsch <m.felsch@pengutronix.de>, Michael Tretter <m.tretter@pengutronix.de>, 
	linux-kernel@vger.kernel.org
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On Thu, Apr 25, 2024 at 4:19=E2=80=AFAM Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
>
> On 12.02.2024 00:09, Adam Ford wrote:
> > When using video sync pulses, the HFP, HBP, and HSA are divided between
> > the available lanes if there is more than one lane.  For certain
> > timings and lane configurations, the HFP may not be evenly divisible.
> > If the HFP is rounded down, it ends up being too small which can cause
> > some monitors to not sync properly. In these instances, adjust htotal
> > and hsync to round the HFP up, and recalculate the htotal.
> >
> > Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL =
i.MX8MM with HDMI monitor
> > Signed-off-by: Adam Ford <aford173@gmail.com>
>
> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>

Thank you very much for testing!

>
> > ---
> > V2:  No changes
> >
> > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/br=
idge/samsung-dsim.c
> > index 8476650c477c..52939211fe93 100644
> > --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> > @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_=
bridge *bridge,
> >               adjusted_mode->flags |=3D (DRM_MODE_FLAG_PHSYNC | DRM_MOD=
E_FLAG_PVSYNC);
> >       }
> >
> > +     /*
> > +      * When using video sync pulses, the HFP, HBP, and HSA are divide=
d between
> > +      * the available lanes if there is more than one lane.  For certa=
in
> > +      * timings and lane configurations, the HFP may not be evenly div=
isible.
> > +      * If the HFP is rounded down, it ends up being too small which c=
an cause
> > +      * some monitors to not sync properly. In these instances, adjust=
 htotal
> > +      * and hsync to round the HFP up, and recalculate the htotal. Thr=
ough trial
> > +      * and error, it appears that the HBP and HSA do not appearto nee=
d the same
> > +      * correction that HFP does.
> > +      */
> > +     if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lane=
s > 1) {

Frieder  &  Marek S,

Marek V is proposing we eliminate the check against the flags and do
it unconditionally.  If I send you both a different patch, would you
be willing to try them on your platforms?  I don't want to risk
breaking a board.
I used the check above from the NXP downstream kernel, so it felt
safe, but I am not as familiar with the different DSI modes, so I am
not sure what the impact would be if this read:

 if (dsi->lanes > 1) {

Does anyone else have an opinion on this?
> > +             int hfp =3D adjusted_mode->hsync_start - adjusted_mode->h=
display;
> > +             int remainder =3D hfp % dsi->lanes;
> > +
> > +             if (remainder) {
> > +                     adjusted_mode->hsync_start +=3D remainder;
> > +                     adjusted_mode->hsync_end   +=3D remainder;
> > +                     adjusted_mode->htotal      +=3D remainder;
> > +             }
> > +     }
> > +
> >       return 0;
> >   }
> >
>
> Best regards
> --
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
>