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References: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com>
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In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-1-67cff4271d1d@rivosinc.com>
From: Guo Ren <guoren@kernel.org>
Date: Fri, 26 Apr 2024 16:15:25 +0800
Message-ID: <CAJF2gTTeGBuL4S3cKV87w-TJTa+ZmOaPiT=+uor-PzL9jYTWAg@mail.gmail.com>
Subject: Re: [PATCH v3 01/17] riscv: cpufeature: Fix thead vector hwcap removal
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
	Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, 
	Albert Ou <aou@eecs.berkeley.edu>, Conor Dooley <conor+dt@kernel.org>, 
	Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, 
	Samuel Holland <samuel@sholland.org>, Conor Dooley <conor.dooley@microchip.com>, 
	Evan Green <evan@rivosinc.com>, =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, 
	Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>, linux-riscv@lists.infradead.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	Palmer Dabbelt <palmer@rivosinc.com>, linux-arm-kernel@lists.infradead.org, 
	linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, 
	linux-kselftest@vger.kernel.org
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On Sun, Apr 21, 2024 at 9:04=E2=80=AFAM Charlie Jenkins <charlie@rivosinc.c=
om> wrote:
>
> The riscv_cpuinfo struct that contains mvendorid and marchid is not
> populated until all harts are booted which happens after the DT parsing.
> Use the vendorid/archid values from the DT if available or assume all
> harts have the same values as the boot hart as a fallback.
>
> Fixes: d82f32202e0d ("RISC-V: Ignore V from the riscv,isa DT property on =
older T-Head CPUs")
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/include/asm/sbi.h   |  2 ++
>  arch/riscv/kernel/cpu.c        | 40 ++++++++++++++++++++++++++++++++++++=
----
>  arch/riscv/kernel/cpufeature.c | 12 ++++++++++--
>  3 files changed, 48 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 6e68f8dff76b..0fab508a65b3 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -370,6 +370,8 @@ static inline int sbi_remote_fence_i(const struct cpu=
mask *cpu_mask) { return -1
>  static inline void sbi_init(void) {}
>  #endif /* CONFIG_RISCV_SBI */
>
> +unsigned long riscv_get_mvendorid(void);
> +unsigned long riscv_get_marchid(void);
>  unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
>  unsigned long riscv_cached_marchid(unsigned int cpu_id);
>  unsigned long riscv_cached_mimpid(unsigned int cpu_id);
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index d11d6320fb0d..c1f3655238fd 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -139,6 +139,34 @@ int riscv_of_parent_hartid(struct device_node *node,=
 unsigned long *hartid)
>         return -1;
>  }
>
> +unsigned long __init riscv_get_marchid(void)
> +{
> +       struct riscv_cpuinfo *ci =3D this_cpu_ptr(&riscv_cpuinfo);
> +
> +#if IS_ENABLED(CONFIG_RISCV_SBI)
> +       ci->marchid =3D sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
> +#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
> +       ci->marchid =3D csr_read(CSR_MARCHID);
> +#else
> +       ci->marchid =3D 0;
> +#endif
> +       return ci->marchid;
> +}
> +
> +unsigned long __init riscv_get_mvendorid(void)
> +{
> +       struct riscv_cpuinfo *ci =3D this_cpu_ptr(&riscv_cpuinfo);
> +
> +#if IS_ENABLED(CONFIG_RISCV_SBI)
> +       ci->mvendorid =3D sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
> +#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
> +       ci->mvendorid =3D csr_read(CSR_MVENDORID);
> +#else
> +       ci->mvendorid =3D 0;
> +#endif
> +       return ci->mvendorid;
> +}
> +
>  DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
>
>  unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
> @@ -170,12 +198,16 @@ static int riscv_cpuinfo_starting(unsigned int cpu)
>         struct riscv_cpuinfo *ci =3D this_cpu_ptr(&riscv_cpuinfo);
>
>  #if IS_ENABLED(CONFIG_RISCV_SBI)
> -       ci->mvendorid =3D sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
> -       ci->marchid =3D sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
> +       if (!ci->mvendorid)
> +               ci->mvendorid =3D sbi_spec_is_0_1() ? 0 : sbi_get_mvendor=
id();
> +       if (!ci->marchid)
> +               ci->marchid =3D sbi_spec_is_0_1() ? 0 : sbi_get_marchid()=
;
>         ci->mimpid =3D sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
>  #elif IS_ENABLED(CONFIG_RISCV_M_MODE)
> -       ci->mvendorid =3D csr_read(CSR_MVENDORID);
> -       ci->marchid =3D csr_read(CSR_MARCHID);
> +       if (!ci->mvendorid)
> +               ci->mvendorid =3D csr_read(CSR_MVENDORID);
> +       if (!ci->marchid)
> +               ci->marchid =3D csr_read(CSR_MARCHID);
>         ci->mimpid =3D csr_read(CSR_MIMPID);
>  #else
>         ci->mvendorid =3D 0;
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeatur=
e.c
> index 3ed2359eae35..c6e27b45e192 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -490,6 +490,8 @@ static void __init riscv_fill_hwcap_from_isa_string(u=
nsigned long *isa2hwcap)
>         struct acpi_table_header *rhct;
>         acpi_status status;
>         unsigned int cpu;
> +       u64 boot_vendorid;
> +       u64 boot_archid;
>
>         if (!acpi_disabled) {
>                 status =3D acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
> @@ -497,6 +499,13 @@ static void __init riscv_fill_hwcap_from_isa_string(=
unsigned long *isa2hwcap)
>                         return;
>         }
>
> +       /*
> +        * Naively assume that all harts have the same mvendorid/marchid =
as the
> +        * boot hart.
> +        */
> +       boot_vendorid =3D riscv_get_mvendorid();
> +       boot_archid =3D riscv_get_marchid();
> +
>         for_each_possible_cpu(cpu) {
>                 struct riscv_isainfo *isainfo =3D &hart_isa[cpu];
>                 unsigned long this_hwcap =3D 0;
> @@ -544,8 +553,7 @@ static void __init riscv_fill_hwcap_from_isa_string(u=
nsigned long *isa2hwcap)
>                  * CPU cores with the ratified spec will contain non-zero
>                  * marchid.
>                  */
> -               if (acpi_disabled && riscv_cached_mvendorid(cpu) =3D=3D T=
HEAD_VENDOR_ID &&
> -                   riscv_cached_marchid(cpu) =3D=3D 0x0) {
> +               if (acpi_disabled && boot_vendorid =3D=3D THEAD_VENDOR_ID=
 && boot_archid =3D=3D 0x0) {
LGTM!
Reviewed-by: Guo Ren <guoren@kernel.org>

>                         this_hwcap &=3D ~isa2hwcap[RISCV_ISA_EXT_v];
>                         clear_bit(RISCV_ISA_EXT_v, isainfo->isa);
>                 }
>
> --
> 2.44.0
>


--=20
Best Regards
 Guo Ren