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Date: Fri, 26 Apr 2024 17:21:16 +0100
From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Evan Green <evan@rivosinc.com>,
	=?iso-8859-1?Q?Cl=E9ment_L=E9ger?= <cleger@rivosinc.com>,
	Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>,
	linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
	linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v3 04/17] riscv: vector: Use vlenb from DT
Message-ID: <20240426-unfixed-mournful-0a71fb3972b4@spud>
References: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com>
 <20240420-dev-charlie-support_thead_vector_6_9-v3-4-67cff4271d1d@rivosinc.com>
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On Fri, Apr 26, 2024 at 04:17:52PM +0100, Conor Dooley wrote:
> On Sat, Apr 20, 2024 at 06:04:36PM -0700, Charlie Jenkins wrote:
> > If vlenb is provided in the device tree, prefer that over reading the
> > vlenb csr.
> >=20
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > ---
> >  arch/riscv/include/asm/cpufeature.h |  2 ++
> >  arch/riscv/kernel/cpufeature.c      | 26 ++++++++++++++++++++++++++
> >  arch/riscv/kernel/vector.c          | 13 +++++++++----
> >  3 files changed, 37 insertions(+), 4 deletions(-)
> >=20
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/a=
sm/cpufeature.h
> > index 347805446151..809f61ffb667 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> >  /* Per-cpu ISA extensions. */
> >  extern struct riscv_isainfo hart_isa[NR_CPUS];
> > =20
> > +extern u32 riscv_vlenb_dt[NR_CPUS];
> > +
> >  void riscv_user_isa_enable(void);
> > =20
> >  #if defined(CONFIG_RISCV_MISALIGNED)
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeat=
ure.c
> > index c6e27b45e192..48874aac4871 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) _=
_read_mostly;
> >  /* Per-cpu ISA extensions. */
> >  struct riscv_isainfo hart_isa[NR_CPUS];
> > =20
> > +u32 riscv_vlenb_dt[NR_CPUS];
> > +
> >  /**
> >   * riscv_isa_extension_base() - Get base extension word
> >   *
> > @@ -656,6 +658,28 @@ static int __init riscv_isa_fallback_setup(char *_=
_unused)
> >  early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> >  #endif
> > =20
> > +static void riscv_set_vlenb_from_dt(void)
>=20
> I'd expect to see a name here that had "of" in it, not "dt".

Also, "set" - I think "get" is more suitable here given that this
doesn't actually set the vlen, we only do any setting later on in
riscv_v_set_vsize().

>=20
> > +{
> > +	int cpu;
> > +
> > +	for_each_possible_cpu(cpu) {
> > +		struct device_node *cpu_node;
> > +
> > +		cpu_node =3D of_cpu_device_node_get(cpu);
> > +		if (!cpu_node) {
> > +			pr_warn("Unable to find cpu node\n");
> > +			continue;
> > +		}
> > +
> > +		if (!of_property_read_u32(cpu_node, "riscv,vlenb", &riscv_vlenb_dt[c=
pu])) {
> > +			of_node_put(cpu_node);
> > +			continue;
> > +		}
> > +
> > +		of_node_put(cpu_node);
> > +	}
> > +}
> > +
> >  void __init riscv_fill_hwcap(void)
> >  {
> >  	char print_str[NUM_ALPHA_EXTS + 1];
> > @@ -675,6 +699,8 @@ void __init riscv_fill_hwcap(void)
> >  	} else {
> >  		int ret =3D riscv_fill_hwcap_from_ext_list(isa2hwcap);
> > =20
> > +		riscv_set_vlenb_from_dt();
>=20
> Hmm, I think we can go a step further here. We know all of the CPUs
> widths by the time we get to the first call to riscv_v_setup_vsize(), can
> we examine the whole list and decide not to enable vector if they do
> not match, rather than continuing and failing to online CPUs that having
> the mismatched size?
>=20
> I guess that can go into the `if (elf_hwcap & COMPAT_HWCAP_ISA_V)`
> condition we already have, and would require clearing the bit from the
> mask we have at the moment.
>=20
> Cheers,
> Conor.
>=20
> > +
> >  		if (ret && riscv_isa_fallback) {
> >  			pr_info("Falling back to deprecated \"riscv,isa\"\n");
> >  			riscv_fill_hwcap_from_isa_string(isa2hwcap);
> > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> > index 6727d1d3b8f2..fb7f3ca80d9e 100644
> > --- a/arch/riscv/kernel/vector.c
> > +++ b/arch/riscv/kernel/vector.c
> > @@ -32,11 +32,16 @@ EXPORT_SYMBOL_GPL(riscv_v_vsize);
> >  int riscv_v_setup_vsize(void)
> >  {
> >  	unsigned long this_vsize;
> > +	int cpu =3D smp_processor_id();
> > =20
> > -	/* There are 32 vector registers with vlenb length. */
> > -	riscv_v_enable();
> > -	this_vsize =3D csr_read(CSR_VLENB) * 32;
> > -	riscv_v_disable();
> > +	if (riscv_vlenb_dt[cpu]) {
> > +		this_vsize =3D riscv_vlenb_dt[cpu];
>=20
> > +	} else {
> > +		/* There are 32 vector registers with vlenb length. */
> > +		riscv_v_enable();
> > +		this_vsize =3D csr_read(CSR_VLENB) * 32;
> > +		riscv_v_disable();
> > +	}
> > =20
> >  	if (!riscv_v_vsize) {
> >  		riscv_v_vsize =3D this_vsize;
> >=20
> > --=20
> > 2.44.0
> >=20


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