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bh=O/bTlpjmn7jvv06zXkXwL7+2GnLGg8WPp/qSEgcnySE=; b=l6 MH/6rX/78seSbNTNrk2jUqdjFOLStFuJIIeupkVy4LvoA6VsFf0E3QsBkGCw72GAT+CkaxZe6nHPO BvFx0PPphMg0J90YCYePpgzULbvASU3EDrHfMjAc9sUOXEdZ/lpR1TWOZE/Aw2BtdNJjnfKLCWzsh 4vjXDOUvDyZcHLw=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1s0p7X-00E9zz-Q3; Sat, 27 Apr 2024 22:58:07 +0200 Date: Sat, 27 Apr 2024 22:58:07 +0200 From: Andrew Lunn To: =?iso-8859-1?Q?Ram=F3n?= Nordin Rodriguez Cc: Parthiban Veerasooran , davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, saeedm@nvidia.com, anthony.l.nguyen@intel.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, corbet@lwn.net, linux-doc@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, horatiu.vultur@microchip.com, ruanjinjie@huawei.com, steen.hegelund@microchip.com, vladimir.oltean@nxp.com, UNGLinuxDriver@microchip.com, Thorsten.Kummermehr@microchip.com, Pier.Beruto@onsemi.com, Selvamani.Rajagopal@onsemi.com, Nicolas.Ferre@microchip.com, benjamin.bigler@bernformulastudent.ch Subject: Re: [PATCH net-next v4 11/12] microchip: lan865x: add driver support for Microchip's LAN865X MAC-PHY Message-ID: <50b7cb69-61c0-45a2-9a48-4160b2d1e24c@lunn.ch> References: <20240418125648.372526-1-Parthiban.Veerasooran@microchip.com> <20240418125648.372526-12-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Sat, Apr 27, 2024 at 09:35:06PM +0200, Ram?n Nordin Rodriguez wrote: > I'm running a dual lan8650 setup, neither IC passed the sw reset in the > oa_tc.c module, I need to pull the reset pin low to reset the pin before > the rest of the init stuff happens. > > The datasheet recommends not doing a sw reset, excerpt from section > 4.1.1.3 Software Reset > "Note: The SW_RESET bit of the Clause 22 Basic Control register will reset only the internal PHY, not > the entire device. This PHY only reset is not recommended for use. If such a reset is detected, by > reading the RESETC bit of the STS2 register, reset the entire device." That is not so good. The PHY driver does not know the PHY is embedded within another device. It has no idea of RESETC bit in STS2. Looking at the phy driver, i don't actually seeing it using genphy_soft_reset(). Do you see a code path where this could actually be an issue? Supporting a hardware reset does however make sense. It would be best if you submitted a proper clean patch. It can be added to the end of this series, keeping you as author. Andrew