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([178.197.223.16]) by smtp.gmail.com with ESMTPSA id u8-20020a170906654800b00a58f15b070dsm2556560ejn.43.2024.04.29.10.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 10:28:54 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= Cc: Krzysztof Kozlowski , Tudor Ambarus , Will McVicker , Sam Protsenko , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 0/2] clock support for Samsung Exynos pin controller (Google Tensor gs101) Date: Mon, 29 Apr 2024 19:28:50 +0200 Message-ID: <171441172281.306662.17546797534297489946.b4-ty@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@linaro.org> References: <20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Fri, 26 Apr 2024 14:25:13 +0100, André Draszik wrote: > This series enables clock support on the Samsung Exynos pin controller > driver. > > This is required on Socs like Google Tensor gs101, which implement > fine-grained clock control / gating, and as such a running bus clock is > required for register access to work. > > [...] Applied, thanks! [1/2] dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clock https://git.kernel.org/pinctrl/samsung/c/dff9f3fb6ba4f74eb805bc172cc16ff2c91648bf [2/2] pinctrl: samsung: support a bus clock https://git.kernel.org/pinctrl/samsung/c/f9c74474797351c60e009ebc59a798fcfd93ee57 Best regards, -- Krzysztof Kozlowski