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Mon, 29 Apr 2024 10:45:55 -0700 (PDT) Message-ID: <479aeb87-ddc1-421a-a451-d9e62893eef5@linaro.org> Date: Mon, 29 Apr 2024 19:45:54 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/2] clock support for Samsung Exynos pin controller (Google Tensor gs101) To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa , Peter Griffin , =?UTF-8?Q?Andr=C3=A9_Draszik?= Cc: Tudor Ambarus , Will McVicker , Sam Protsenko , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@linaro.org> <171441172281.306662.17546797534297489946.b4-ty@linaro.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 29/04/2024 19:28, Krzysztof Kozlowski wrote: > > On Fri, 26 Apr 2024 14:25:13 +0100, André Draszik wrote: >> This series enables clock support on the Samsung Exynos pin controller >> driver. >> >> This is required on Socs like Google Tensor gs101, which implement >> fine-grained clock control / gating, and as such a running bus clock is >> required for register access to work. >> Where's the DTS? Best regards, Krzysztof