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Date: Mon, 29 Apr 2024 21:38:07 -0000
From: "tip-bot2 for Daniel J Blueman" <tip-bot2@linutronix.de>
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Subject: [tip: x86/timers] x86/tsc: Trust initial offset in architectural
 TSC-adjust MSRs
Cc: Daniel J Blueman <daniel@quora.org>, Thomas Gleixner <tglx@linutronix.de>,
 Steffen Persvold <sp@numascale.com>,
 James Cleverdon <james.cleverdon.external@eviden.com>,
 Dimitri Sivanich <sivanich@hpe.com>, Prarit Bhargava <prarit@redhat.com>,
 x86@kernel.org, linux-kernel@vger.kernel.org
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The following commit has been merged into the x86/timers branch of tip:

Commit-ID:     455f9075f14484f358b3c1d6845b4a438de198a7
Gitweb:        https://git.kernel.org/tip/455f9075f14484f358b3c1d6845b4a438de198a7
Author:        Daniel J Blueman <daniel@quora.org>
AuthorDate:    Fri, 19 Apr 2024 16:51:46 +08:00
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Mon, 29 Apr 2024 23:27:16 +02:00

x86/tsc: Trust initial offset in architectural TSC-adjust MSRs

When the BIOS configures the architectural TSC-adjust MSRs on secondary
sockets to correct a constant inter-chassis offset, after Linux brings the
cores online, the TSC sync check later resets the core-local MSR to 0,
triggering HPET fallback and leading to performance loss.

Fix this by unconditionally using the initial adjust values read from the
MSRs. Trusting the initial offsets in this architectural mechanism is a
better approach than special-casing workarounds for specific platforms.

Signed-off-by: Daniel J Blueman <daniel@quora.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Steffen Persvold <sp@numascale.com>
Reviewed-by: James Cleverdon <james.cleverdon.external@eviden.com>
Reviewed-by: Dimitri Sivanich <sivanich@hpe.com>
Reviewed-by: Prarit Bhargava <prarit@redhat.com>
Link: https://lore.kernel.org/r/20240419085146.175665-1-daniel@quora.org
---
 arch/x86/kernel/tsc_sync.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 1123ef3..4334033 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -193,11 +193,9 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
 	cur->warned = false;
 
 	/*
-	 * If a non-zero TSC value for socket 0 may be valid then the default
-	 * adjusted value cannot assumed to be zero either.
+	 * The default adjust value cannot be assumed to be zero on any socket.
 	 */
-	if (tsc_async_resets)
-		cur->adjusted = bootval;
+	cur->adjusted = bootval;
 
 	/*
 	 * Check whether this CPU is the first in a package to come up. In