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From: yunhui cui <cuiyunhui@bytedance.com>
Date: Tue, 30 Apr 2024 11:16:15 +0800
Message-ID: <CAEEQ3w=FJMzkL3_if1rQcHCUu0C9PVJzL3D3yytNLr-y3YS5nw@mail.gmail.com>
Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize
 cacheinfo's level and type from ACPI PPTT
To: Jeremy Linton <jeremy.linton@arm.com>, Palmer Dabbelt <palmer@rivosinc.com>, 
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org, 
	linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, 
	linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com, 
	john.garry@huawei.com, Jonathan.Cameron@huawei.com, pierre.gondois@arm.com, 
	sudeep.holla@arm.com, tiantao6@huawei.com
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Hi Palmer,

Gentle ping...

On Tue, Apr 23, 2024 at 7:03=E2=80=AFPM yunhui cui <cuiyunhui@bytedance.com=
> wrote:
>
> Hi Palmer,
>
> On Fri, Apr 19, 2024 at 11:29=E2=80=AFPM Jeremy Linton <jeremy.linton@arm=
com> wrote:
> >
> > Hi,
> >
> > On 4/17/24 22:43, Yunhui Cui wrote:
> > > Before cacheinfo can be built correctly, we need to initialize level
> > > and type. Since RSIC-V currently does not have a register group that
> > > describes cache-related attributes like ARM64, we cannot obtain them
> > > directly, so now we obtain cache leaves from the ACPI PPTT table
> > > (acpi_get_cache_info()) and set the cache type through split_levels.
> > >
> > > Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
> > > Suggested-by: Sudeep Holla <sudeep.holla@arm.com>
> > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > > ---
> > >   arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> > >   1 file changed, 22 insertions(+)
> > >
> > > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cachei=
nfo.c
> > > index 30a6878287ad..e47a1e6bd3fe 100644
> > > --- a/arch/riscv/kernel/cacheinfo.c
> > > +++ b/arch/riscv/kernel/cacheinfo.c
> > > @@ -6,6 +6,7 @@
> > >   #include <linux/cpu.h>
> > >   #include <linux/of.h>
> > >   #include <asm/cacheinfo.h>
> > > +#include <linux/acpi.h>
> > >
> > >   static struct riscv_cacheinfo_ops *rv_cache_ops;
> > >
> > > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> > >       struct device_node *prev =3D NULL;
> > >       int levels =3D 1, level =3D 1;
> > >
> > > +     if (!acpi_disabled) {
> > > +             int ret, fw_levels, split_levels;
> > > +
> > > +             ret =3D acpi_get_cache_info(cpu, &fw_levels, &split_lev=
els);
> > > +             if (ret)
> > > +                     return ret;
> > > +
> > > +             BUG_ON((split_levels > fw_levels) ||
> > > +                    (split_levels + fw_levels > this_cpu_ci->num_lea=
ves));
> > > +
> > > +             for (; level <=3D this_cpu_ci->num_levels; level++) {
> > > +                     if (level <=3D split_levels) {
> > > +                             ci_leaf_init(this_leaf++, CACHE_TYPE_DA=
TA, level);
> > > +                             ci_leaf_init(this_leaf++, CACHE_TYPE_IN=
ST, level);
> > > +                     } else {
> > > +                             ci_leaf_init(this_leaf++, CACHE_TYPE_UN=
IFIED, level);
> > > +                     }
> > > +             }
> > > +             return 0;
> > > +     }
> > > +
> > >       if (of_property_read_bool(np, "cache-size"))
> > >               ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > >       if (of_property_read_bool(np, "i-cache-size"))
> >
> > Yes, looks good.
> >
> > Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
> >
> >
> >
> > Thanks,
>
> Could you help review this patchset? Thanks.
>
> Thanks,
> Yunhui

Thanks,
Yunhui