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29 Apr 2024 20:49:57 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang Cc: linux-kernel@vger.kernel.org, Dapeng Mi , Dapeng Mi Subject: [PATCH 1/2] perf/x86: Remove perf_events_lapic_init() calling from x86_pmu_enable() Date: Tue, 30 Apr 2024 11:56:52 +0800 Message-Id: <20240430035653.19457-1-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit perf_events_lapic_init() helper is called to configure PMI to NMI vector and clear MASK bit simultaneously by writing APIC_LVTPC MSR. It's called firstly to initialize APIC_LVTPC MSR by init_hw_perf_events(), and the PMI handler would always to clear the MASK bit in APIC_LVTPC MSR by writing APIC_LVTPC MSR directly. So it becomes unnecessary to call perf_events_lapic_init() again in x86_pmu_enable(), and worse x86_pmu_enable() could be called very frequently in some scenarios with very high context-switches. This would cause performance overhead which can't be ignored especially in KVM guest environment since frequent APIC_LVTPC writing would cause huge number of VM-Exits. For example, in guest environment Geekbench score (running multiplxing perf-stat command in background) increases 1% and perf-sched benchmark increases 7% after removing perf_events_lapic_init() calling from x86_pmu_enable(). Signed-off-by: Dapeng Mi --- arch/x86/events/core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 5b0dd07b1ef1..580923443813 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1347,7 +1347,6 @@ static void x86_pmu_enable(struct pmu *pmu) x86_pmu_start(event, PERF_EF_RELOAD); } cpuc->n_added = 0; - perf_events_lapic_init(); } cpuc->enabled = 1; base-commit: 854dd99b5ddc9d90e31e5f112462a5994dd31810 -- 2.40.1