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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 29/04/24 11:53, Pin-yen Lin ha scritto: > Set off-on-delay-us to 500000 us for pp3300_mipibrdg to make sure it > complies with the panel sequence. Explicit configuration on the > regulator node is required because mt8192-asurada uses the same power > supply for the panel and the anx7625 DP bridge. So powering on/off the > DP bridge could break the power sequence requirement for the panel. > > Fixes: f9f00b1f6b9b ("arm64: dts: mediatek: asurada: Add display regulators") > Signed-off-by: Pin-yen Lin > Uhm, there might be more to it - I don't think that this should ever happen. The regulator is refcounted, so... * Bridge on: panel goes off, but regulator doesn't turn off (refcount=1) * Panel resume -> sequence respected (refcount=2 -> wait -> more vregs, etc) * Bridge off: panel is already off (refcount=0) * Bridge resume -> refcount=1, no panel commands yet * Panel resume -> refcount=2, wait -> more vregs, etc Can you please describe the issue that you're getting? Cheers, Angelo > --- > > arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi > index 7a704246678f..08d71ddf3668 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi > @@ -147,6 +147,7 @@ pp3300_mipibrdg: regulator-3v3-mipibrdg { > regulator-boot-on; > gpio = <&pio 127 GPIO_ACTIVE_HIGH>; > vin-supply = <&pp3300_g>; > + off-on-delay-us = <500000>; > }; > > /* separately switched 3.3V power rail */