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AJvYcCVELQGTOH2brh4nDx+UQrsU7XvEC5z5A7x8bTQ5pxWfMLRYxRcJyDZLH4AZ78QE+MmgTPnrRtBUu1fUPrTlHc9FQpZmK91Jm0KmcFHb9UC4++riEQnqF4J6z6L1p0wmBwaSR8a3S7lILtDNR5iR X-Gm-Message-State: AOJu0YyYSY9La1JGAr5jM/zWttEKZdozExh8s3HgWjS0wcInIdOc5TKn 0MmqKVxRImhdDsSxCtSMQPQpGoNXFxBx3ooxsB0NAprmcIQ78yGg X-Received: by 2002:a17:90a:9317:b0:2b2:a6e9:400c with SMTP id p23-20020a17090a931700b002b2a6e9400cmr1164428pjo.12.1714486504606; Tue, 30 Apr 2024 07:15:04 -0700 (PDT) Received: from prasmi.domain.name ([103.219.60.80]) by smtp.gmail.com with ESMTPSA id az24-20020a17090b029800b0029bacd0f271sm22883227pjb.31.2024.04.30.07.15.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 07:15:03 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v4 0/2] Add IAX45 support for RZ/Five SoC Date: Tue, 30 Apr 2024 15:14:36 +0100 Message-Id: <20240430141438.132838-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Lad Prabhakar Hi All, The IAX45 block on RZ/Five SoC is almost identical to the IRQC bock found on the RZ/G2L family of SoCs. IAX45 performs various interrupt controls including synchronization for the external interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral interrupts output by each module. And it notifies the interrupt to the PLIC. - Select 32 TINT from 82 GPIOINT. - Integration of bus error interrupts from system bus. - Integration of ECC error interrupts from On-chip RAM. - Indicate interrupt status. (NMI, IRQ, TINT, integrated bus error interrupt and integrated ECC error interrupt) - Setting of interrupt detection method. (NMI, IRQ and TINT) - All interrupts are masked by INTMASK. - Mask function for NMI, IRQ and TINT This patch series adds support for IAX45 in the IRQC driver and enables this on RZ/Five SoC. v3->v4 - Renamed rzg2l_irqc_init_helper -> rzg2l_irqc_common_init - Moved the locks into callers for (un)mask and (en/dis)able functions - Collected RB tag from Geert for patch#2 v2->v3 - DTS/I patches dropped from the series as they have been merged into renesas-soc tree - Just using a const from compat string instead of having it in a items - Added RZ/Five specific irqchip v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240129151618.90922-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC irqchip/renesas-rzg2l: Add support for RZ/Five SoC .../renesas,rzg2l-irqc.yaml | 17 +- drivers/irqchip/irq-renesas-rzg2l.c | 148 +++++++++++++++++- 2 files changed, 155 insertions(+), 10 deletions(-) -- 2.34.1