Received-SPF: pass (google.com: domain of linux-kernel+bounces-164411-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
 216.228.117.161 as permitted sender) receiver=protection.outlook.com;
 client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C
Date: Tue, 30 Apr 2024 09:43:49 -0700
From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
CC: <will@kernel.org>, <robin.murphy@arm.com>, <joro@8bytes.org>,
	<thierry.reding@gmail.com>, <vdumpa@nvidia.com>, <jonathanh@nvidia.com>,
	<linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>,
	<linux-arm-kernel@lists.infradead.org>, <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v6 2/6] iommu/arm-smmu-v3: Add CS_NONE quirk
Message-ID: <ZjEfxcSd90ts4XmJ@Asurada-Nvidia>
References: <cover.1714451595.git.nicolinc@nvidia.com>
 <81d79f51c69604a38ea4f72c8ac2c573c52e8609.1714451595.git.nicolinc@nvidia.com>
 <20240430142201.GQ941030@nvidia.com>
 <ZjEcs4rY1HpPz4Oa@Asurada-Nvidia>
 <20240430163733.GT941030@nvidia.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <20240430163733.GT941030@nvidia.com>
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 16:44:08.2092
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: bb6a583d-c25c-4942-22f4-08dc6934c168
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource:
	CH2PEPF0000009E.namprd02.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4270

On Tue, Apr 30, 2024 at 01:37:33PM -0300, Jason Gunthorpe wrote:
> On Tue, Apr 30, 2024 at 09:30:43AM -0700, Nicolin Chen wrote:
> > >  	queue_write(Q_ENT(q, cons), cmd, q->ent_dwords);
> > 
> > Here is the only caller for "msi=false". Maybe we could just do:
> > +	arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons);
> > 
> > So, no need of "bool msi"? It would slightly change the behavior
> > though, a SYNC for ARM_SMMU_OPT_MSIPOLL should be still a SYNC.
> 
> I don't know, I didn't try to figure out what to stick for prod in
> that case. It is probably OK to convert an error entry into a MSI
> sync if it works out?

Yea. I think it should be okay. I will try a hack with an illegal
command to test it out.

Nicolin