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AJvYcCWyfK6k955o/zYKOwuozYAJKCjVWuB/soAQT9OdEsTtCZVVkmRzbnA5KOldZRCSz4XqWCGkag4U4Cak5WDyzMHQa33WKrx9hlxDvsPE X-Gm-Message-State: AOJu0YzprV1xNeDHHHUkC4fXZhn04pPTkWXb0TzMGsaIFcSYWegXHBQR ofGi9FXX5W1gjsoC8dqErR5fBWsZ8AScqxC8f1HuPF3OjxG39iyRHwehqLIr6IBKW/PqsLL040R L5rRvftF3krFZkNBGy9gLy+44qSr7BaGpX3fq8g== X-Received: by 2002:a25:8409:0:b0:de5:a062:ba8d with SMTP id u9-20020a258409000000b00de5a062ba8dmr309405ybk.11.1714499427026; Tue, 30 Apr 2024 10:50:27 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <1714494711-10322-1-git-send-email-quic_msarkar@quicinc.com> <1714494711-10322-3-git-send-email-quic_msarkar@quicinc.com> In-Reply-To: <1714494711-10322-3-git-send-email-quic_msarkar@quicinc.com> From: Dmitry Baryshkov Date: Tue, 30 Apr 2024 20:50:15 +0300 Message-ID: Subject: Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Set max link speed to gen4 for ep pcie To: Mrinmay Sarkar Cc: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_schintav@quicinc.com, Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" On Tue, 30 Apr 2024 at 19:33, Mrinmay Sarkar wrote: > > Adding this change to set max link speed to gen4 as sa8775p supports > gen4 so that pcie link can be enumerated as gen4. Previous patches mentioned stability issues. Were they solved? > > Signed-off-by: Mrinmay Sarkar > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 0c52180..aad2cd7 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -3730,7 +3730,7 @@ > power-domains = <&gcc PCIE_0_GDSC>; > phys = <&pcie0_phy>; > phy-names = "pciephy"; > - max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ > + max-link-speed = <4>; > num-lanes = <2>; > > status = "disabled"; > @@ -3888,7 +3888,7 @@ > power-domains = <&gcc PCIE_1_GDSC>; > phys = <&pcie1_phy>; > phy-names = "pciephy"; > - max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ I think you've just sent a patchset which adds this node. Is there any reason for setting the max-link-speed to 3 just to change it to 4 immediately? > + max-link-speed = <4>; > num-lanes = <4>; > > status = "disabled"; > -- > 2.7.4 > > -- With best wishes Dmitry