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From: Jassi Brar <jassisinghbrar@gmail.com>
Date: Tue, 30 Apr 2024 21:14:32 -0500
Message-ID: <CABb+yY2mjc0BmvdUxZvkEvFMS30g=h5F7aHEKogfH9=W0C1a2w@mail.gmail.com>
Subject: Re: [PATCH V4 2/5] mailbox: Add support for QTI CPUCP mailbox controller
To: Sibi Sankar <quic_sibis@quicinc.com>
Cc: sudeep.holla@arm.com, cristian.marussi@arm.com, andersson@kernel.org, 
	konrad.dybcio@linaro.org, robh+dt@kernel.org, 
	krzysztof.kozlowski+dt@linaro.org, dmitry.baryshkov@linaro.org, 
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, 
	devicetree@vger.kernel.org, quic_rgottimu@quicinc.com, 
	quic_kshivnan@quicinc.com, conor+dt@kernel.org, quic_gkohli@quicinc.com, 
	quic_nkela@quicinc.com, quic_psodagud@quicinc.com, abel.vesa@linaro.org
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On Mon, Apr 22, 2024 at 11:41=E2=80=AFAM Sibi Sankar <quic_sibis@quicinc.co=
m> wrote:
>
> Add support for CPUSS Control Processor (CPUCP) mailbox controller,
> this driver enables communication between AP and CPUCP by acting as
> a doorbell between them.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---

Do you want to add an entry in the MAINTAINERS ?

> diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpu=
cp-mbox.c
 .....
> +static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data)
> +{
> +       struct qcom_cpucp_mbox *cpucp =3D data;
> +       struct mbox_chan *chan;
> +       unsigned long flags;
> +       u64 status;
> +       u32 val;
> +       int i;
> +
The variables flags, val and chan are better inside the for loop below.

> +       status =3D readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
> +
> +       for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN=
_SUPPORTED) {
> +               val =3D readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) =
+ APSS_CPUCP_MBOX_CMD_OFF);
> +               chan =3D &cpucp->chans[i];
> +               /* Provide mutual exclusion with changes to chan->cl */
> +               spin_lock_irqsave(&chan->lock, flags);
> +               if (chan->cl)
> +                       mbox_chan_received_data(chan, &val);
> +               writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR)=
;
> +               spin_unlock_irqrestore(&chan->lock, flags);
> +       }
> +
> +       return IRQ_HANDLED;
> +}
> +

Thanks
Jassi