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Wed, 1 May 2024 10:23:03 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B0E6C53803; Wed, 1 May 2024 10:22:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ty3MpEbR" Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA4FA33CD1; Wed, 1 May 2024 10:22:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714558971; cv=none; b=UxzcaQPvdAfNjl6y0IWXlCNWLKmJoLQu6vqO6LUAr0+lMoS5ez5HBx7B/NOZWx8dg7PTMAhGHNSmaRPsVw4Ribblf/w5+PSkgGVuqg7yOWTAroR+81c3lOZ0gS4EcHWTRjdsPDz1+JlJL+izE692riIfArAP7HdtJxX4nsYiwkM= ARC-Message-Signature:i=1; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 01/05/2024 06:28, Alexandru Gagniuc wrote: > There are four PCIe ports on IPQ9574, pcie0 thru pcie3. This series > addresses pcie2, which is a gen3x2 port. The board I have only uses > pcie2, and that's the only one enabled in this series. pcie3 is added > as a special request, but is untested. > > I believe this makes sense as a monolithic series, as the individual > pieces are not that useful by themselves. > > In v2, I've had some issues regarding the dt schema checks. For > transparency, I used the following test invocations to test: > > make dt_binding_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml > make dtbs_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml > > Changes since v3: > - "const"ify .hw.init fields for the PCIE pipe clocks > - Used pciephy_v5_regs_layout instead of v4 in phy-qcom-qmp-pcie.c > - Included Manivannan's patch for qcom-pcie.c clocks > - Dropped redundant comments in "ranges" and "interrupt-map" of pcie2. > - Added pcie3 and pcie3_phy dts nodes > - Moved snoc and anoc clocks to PCIe controller from PHY > Three postings within short time... Allow people to actually review your code. Please wait 24h before posting new version. Include entire feedback and all tags. Explain why you ignore/skip some tags. Best regards, Krzysztof