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b=ipJrZgyTXzIChQidmJnBt4o8esmYwm9uia7BinYTSuO9XL4iQ/JVxec8eGphu4TKlIRPID2LDbmHrUYzhmDH0VpMqmXoCV5x3/serC2lMICJ5lquyxrbO/G1840IALND62YA11H7kgSppizr7Ax95dlVHFnmVT5TiTICSA9Rtas= Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by DBAPR04MB7432.eurprd04.prod.outlook.com (2603:10a6:10:1a9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.28; Wed, 1 May 2024 12:52:59 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::d30b:44e7:e78e:662d]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::d30b:44e7:e78e:662d%4]) with mapi id 15.20.7519.031; Wed, 1 May 2024 12:52:59 +0000 From: Peng Fan To: Cristian Marussi CC: Rob Herring , "Peng Fan (OSS)" , Linus Walleij , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Sudeep Holla , "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" , "imx@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v2 1/2] dt-bindings: firmware: arm,scmi: Add properties for i.MX95 Pinctrl OEM extensions Thread-Topic: [PATCH v2 1/2] dt-bindings: firmware: arm,scmi: Add properties for i.MX95 Pinctrl OEM extensions Thread-Index: AQHakTp0F0gZzKwEJ0KLehvuXBXWtLF32SuAgADPKOCACauUAIAAClDggAAIwICAAAJ4sA== Date: Wed, 1 May 2024 12:52:59 +0000 Message-ID: References: <20240418-pinctrl-scmi-oem-v1-v2-0-3a555a3c58c3@nxp.com> <20240418-pinctrl-scmi-oem-v1-v2-1-3a555a3c58c3@nxp.com> <20240424193007.GA329896-robh@kernel.org> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 756942b6-aa98-4b17-0a52-08dc69dda120 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 May 2024 12:52:59.1166 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Pe5so5768pul7fmY+pek7fmsLmwuYyWjzs6+bm2e6GiDG+mRJGf42dbmXPd5IQNNo54fmp0X4TmrzLIXByYeaQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7432 > Subject: Re: [PATCH v2 1/2] dt-bindings: firmware: arm,scmi: Add properti= es > for i.MX95 Pinctrl OEM extensions >=20 > On Wed, May 01, 2024 at 12:11:41PM +0000, Peng Fan wrote: > > > Subject: Re: [PATCH v2 1/2] dt-bindings: firmware: arm,scmi: Add > > > properties for i.MX95 Pinctrl OEM extensions > > > > > > On Thu, Apr 25, 2024 at 09:06:00AM +0000, Peng Fan wrote: > > > > Hi Rob, > > > > > > > > > Subject: Re: [PATCH v2 1/2] dt-bindings: firmware: arm,scmi: Add > > > > > properties for i.MX95 Pinctrl OEM extensions > > > > > > > > > > On Thu, Apr 18, 2024 at 10:53:17AM +0800, Peng Fan (OSS) wrote: > > > > > > From: Peng Fan > > > > > > > > > > > > i.MX95 Pinctrl is managed by SCMI firmware using OEM extensions= . > > > > > > This patch is to add i.MX95 Pinctrl OEM extensions properties. > > > > > > > > > > > > Signed-off-by: Peng Fan > > > > > > --- > > > > > > .../devicetree/bindings/firmware/arm,scmi.yaml | 9 ++- > > > > > > .../bindings/firmware/nxp,imx95-scmi-pinctrl.yaml | 66 > > > > > > ++++++++++++++++++++++ > > > > > > 2 files changed, 72 insertions(+), 3 deletions(-) > > > > > > > > > > > > diff --git > > > > > > a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml > > > > > > b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml > > > > > > > > .... > > > > > > > > > > + > > > > > > +title: i.MX System Control and Management Interface (SCMI) > > > > > > +Pinctrl Protocol > > > > > > + > > > > > > +maintainers: > > > > > > + - Peng Fan > > > > > > + > > > > > > +patternProperties: > > > > > > + '[a-f0-9]+$': > > > > > > + type: object > > > > > > + unevaluatedProperties: false > > > > > > + > > > > > > + properties: > > > > > > + pins: > > > > > > + $ref: /schemas/types.yaml#/definitions/string > > > > > > + description: name of the pin > > > > > > + items: > > > > > > + enum: [ daptdi, daptmsswdio, daptclkswclk, daptdotra= ceswo, > > > > > > + gpioio00, gpioio01, gpioio02, gpioio03, > > > > > > + gpioio04, > > > > > > > > > > ioio? > > > > > > > > Yes. The name is exported from SCMI firmware. > > > > > > > > > > > > > > > + gpioio05, gpioio06, gpioio07, gpioio08, gpio= io09, > > > > > > + gpioio10, gpioio11, gpioio12, gpioio13, gpio= io14, > > > > > > + gpioio15, gpioio16, gpioio17, gpioio18, gpio= io19, > > > > > > + gpioio20, gpioio21, gpioio22, gpioio23, gpio= io24, > > > > > > + gpioio25, gpioio26, gpioio27, gpioio28, gpio= io29, > > > > > > + gpioio30, gpioio31, gpioio32, gpioio33, gpio= io34, > > > > > > + gpioio35, gpioio36, gpioio37, ccmclko1, ccmc= lko2, > > > > > > + ccmclko3, ccmclko4, enet1mdc, enet1mdio, ene= t1td3, > > > > > > + enet1td2, enet1td1, enet1td0, enet1txctl, en= et1txc, > > > > > > + enet1rxctl, enet1rxc, enet1rd0, enet1rd1, en= et1rd2, > > > > > > + enet1rd3, enet2mdc, enet2mdio, enet2td3, ene= t2td2, > > > > > > + enet2td1, enet2td0, enet2txctl, enet2txc, en= et2rxctl, > > > > > > + enet2rxc, enet2rd0, enet2rd1, enet2rd2, enet= 2rd3, > > > > > > + sd1clk, sd1cmd, sd1data0, sd1data1, sd1data2= , sd1data3, > > > > > > + sd1data4, sd1data5, sd1data6, sd1data7, sd1s= trobe, > > > > > > + sd2vselect, sd3clk, sd3cmd, sd3data0, sd3dat= a1, > > > > > > + sd3data2, sd3data3, xspi1data0, xspi1data1, = xspi1data2, > > > > > > + xspi1data3, xspi1data4, xspi1data5, xspi1dat= a6, > > > > > > + xspi1data7, xspi1dqs, xspi1sclk, xspi1ss0b, = xspi1ss1b, > > > > > > + sd2cdb, sd2clk, sd2cmd, sd2data0, sd2data1, = sd2data2, > > > > > > + sd2data3, sd2resetb, i2c1scl, i2c1sda, i2c2s= cl, i2c2sda, > > > > > > + uart1rxd, uart1txd, uart2rxd, uart2txd, pdmc= lk, > > > > > > + pdmbitstream0, pdmbitstream1, sai1txfs, sai1= txc, > > > > > > + sai1txd0, sai1rxd0, wdogany, fccuerr0 ] > > > > > > + > > > > > > + nxp,func-id: > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > > > + description: Indicates the PAD connections which > > > > > > + function module > > > > > > > > > > The description makes no sense... > > > > > > > > I will use below description in v3: > > > > For each pin, there are up to 8 muxing options (called ALT modes). > > > > For > > > example: > > > > Select 1 of 5 iomux modes to be used for pad: DAP_TCLK_SWCLK. > > > > 000b - Select mux mode: ALT0 mux port: JTAG_MUX_TCK of instance: > > > > jtag_mux 010b - Select mux mode: ALT2 mux port: CAN4_RX of instance= : > > > > imx95_wakeupmix_top 100b - Select mux mode: ALT4 mux port: > > > > FLEXIO1_FLEXIO30 of instance: imx95_wakeupmix_top 101b - Select > > > > mux > > > > mode: ALT5 mux port: GPIO3_IO30 of instance: imx95_wakeupmix_top > > > 110b > > > > - Select mux mode: ALT6 mux port: LPUART5_CTS_B of instance: > > > imx95_wakeupmix_top The nxp,func-id property is selecting one ALT > mode. > > > > > > > > > > > > > > > + > > > > > > + nxp,pin-conf: > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > > > + description: The PAD configuration > > > > > > > > > > PAD stands for? Or is it pin configuration as the property name s= ays? > > > > > > > > It is pin configuration which includes pull up/down, drive strength= and > etc. > > > > > > > > > > > > > > This is just a raw register values? > > > > > > > > Yes. > > > > > > > > Why can't standard pinctrl properties be > > > > > used here. What's the point of using SCMI pinctrl if you are > > > > > just shuttling register values to SCMI? > > > > > > > > Standard pinctrl properties will need more memory in our SCMI > > > > firmware design. We have limited on-chip memory for SCMI firmware > usage. > > > > > > > > > > So you sort of strip-down the server due to hw constraints, but is > > > it the SCMI server still compliant with the spec ? (as in supporting > > > all the mandatory commands and features for the protocols you > > > decided to > > > support) > > > > Yes, the SCMI server is compliant with the spec. It is the SCMI > > firmware returns num function with value zero, num group with value zer= o. > > > > And only OEM pin configure type supported in our SCMI firmware. > > > > I have posted out v3 following Rob's suggestion, using property > > 'pinmux', but now we could not reuse pinctrl-scmi.c >=20 > As I wrote in a separated thread (only 5 mins ago), if you have written a > distinct SCMI driver to use protocol@19 ops to suit your needs after havi= ng > parsed your DT...why do you want to re-use pinctrl-scmi.c and so create a > dependency between the 2 ? >=20 > The only thing that they have in common is that they are SCMI drivers usi= ng > SCMI Pinctrl protocol@19 operations in their own different way. Yes. I have replied there. I thought to reuse pinctrl-scmi.c with minimal changes, but since the binding changes in v3, I need to made big changes. Anyway I agree with your suggestions to decouple the two drivers. I will do that in v4. Before that, I need wait for dt-maintainers to review the binding changes in v3. Thanks, Peng. >=20 > Thanks, > Cristian