Message-ID: <479E61EA.8000702@intel.com>
Date: Mon, 28 Jan 2008 15:14:50 -0800
From: "Kok, Auke" <auke-jan.h.kok@intel.com>
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To: Pavel Machek <pavel@ucw.cz>
CC: Shaohua Li <shaohua.li@intel.com>, lkml <linux-kernel@vger.kernel.org>,
       linux-pci <linux-pci@atrey.karlin.mff.cuni.cz>,
       Greg KH <greg@kroah.com>,
       "Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>,
       Matthew Wilcox <matthew@wil.cx>
Subject: Re: [PATCH]PCIE ASPM support - takes 3
References: <1200621388.8965.3.camel@sli10-desk.sh.intel.com> <20080124172258.GA5447@ucw.cz>
In-Reply-To: <20080124172258.GA5447@ucw.cz>
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Pavel Machek wrote:
> Hi!
> 
>> v3->v2, fixed the issues Matthew Wilcox raised.
>>
>> PCI Express ASPM defines a protocol for PCI Express components in the D0
>> state to reduce Link power by placing their Links into a low power state
>> and instructing the other end of the Link to do likewise. This
>> capability allows hardware-autonomous, dynamic Link power reduction
>> beyond what is achievable by software-only controlled power management.
>> However, The device should be configured by software appropriately.
>> Enabling ASPM will save power, but will introduce device latency.
> 
> How big is the latency? 1msec? 10msec? 100usec?

the latency is different for each device but the timing is negotiated and the
pci-e spec lists possible timings that can be used. The maximum is (I think...)
64usec but can be as low as 1 or 2 usec.

Auke
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