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Wed, 1 May 2024 09:32:46 -0700 Date: Wed, 1 May 2024 09:32:44 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , , , , , , , , , Subject: Re: [PATCH v6 6/6] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF Message-ID: References: <4ee1f867e838b90a21de16b12cf2e39ba699eab4.1714451595.git.nicolinc@nvidia.com> <20240430170655.GU941030@nvidia.com> <20240501001758.GZ941030@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240501001758.GZ941030@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37E:EE_|LV2PR12MB5824:EE_ X-MS-Office365-Filtering-Correlation-Id: e3db6ebf-846f-409c-b113-08dc69fc5d7f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400014|376005|36860700004|1800799015; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2024 16:32:59.9686 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3db6ebf-846f-409c-b113-08dc69fc5d7f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5824 On Tue, Apr 30, 2024 at 09:17:58PM -0300, Jason Gunthorpe wrote: > On Tue, Apr 30, 2024 at 11:58:44AM -0700, Nicolin Chen wrote: > > > > Has to push everything, across all the iterations of add/submut, onto > > > the same CMDQ otherwise the SYNC won't be properly flushing? > > > > ECMDQ seems to have such a limitation, but VCMDQs can get away > > as HW can insert a SYNC to a queue that doesn't end with a SYNC. > > That seems like a strange thing to do in HW, but I recall you > mentioned it once before. Still, I'm not sure there is any merit in > relying on it? I was hoping to get some idea from the designer. Yet, at this moment, let's say there's likely no merit besides SW can care less and stay simpler, AFAIK. Robin previously remarked that there could be some performance impact from such a feature, so I think adding your patch would be nicer. > > > Something sort of like this as another patch? > > > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > index 268da20baa4e9c..d8c9597878315a 100644 > > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > @@ -357,11 +357,22 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) > > > return 0; > > > } > > > > > > -static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu, > > > - u64 *cmds, int n) > > > +enum required_cmds { > > > + CMDS_ALL, > > > + /* > > > + * Commands will be one of: > > > + * CMDQ_OP_ATC_INV, CMDQ_OP_TLBI_EL2_VA, CMDQ_OP_TLBI_NH_VA, > > > + * CMDQ_OP_TLBI_EL2_ASID, CMDQ_OP_TLBI_NH_ASID, CMDQ_OP_TLBI_S2_IPA, > > > + * CMDQ_OP_TLBI_S12_VMALL, CMDQ_OP_SYNC > > > + */ > > > + CMDS_INVALIDATION, > > > +}; > > > > Hmm, guest-owned VCMDQs don't support EL2 commands. So, it feels > > to be somehow complicated to decouple them further in the callers > > of arm_smmu_cmdq_batch_add(). And I am not sure if there is a use > > case of guest issuing CMDQ_OP_TLBI_S2_IPA/CMDQ_OP_TLBI_S12_VMALL > > either, HW surprisingly supports these two though. > > These are the max commands that could be issued, but they are all > gated based on the feature bits. The ones VCMDQ don't support are not > going to be issued because of the feature bits. You could test and > enforce this when probing the ECMDQ parts. Ah, I see. So cmdqv's probe() could check the smmu->features against ARM_SMMU_FEAT_E2H, and disable VINTF0 right away, in case of guest-owned while E2H is present. And we could do the same for ARM_SMMU_FEAT_TRANS_S2, stating that the driver does not expect use cases of issuing S2 TLBI commands from the guest OS. Thanks Nicolin