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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Thu, 02 May 2024 10:59:36 +0100
Subject: [PATCH v3 9/9] MIPS: CPS: Convert to use debug_ll facilities
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Message-Id: <20240502-mips_debug_ll-v3-9-3b61f30e484c@flygoat.com>
References: <20240502-mips_debug_ll-v3-0-3b61f30e484c@flygoat.com>
In-Reply-To: <20240502-mips_debug_ll-v3-0-3b61f30e484c@flygoat.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, 
 Jiaxun Yang <jiaxun.yang@flygoat.com>, 
 =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>

debug_ll replaced CPS's custom NS16550 printing functions
for dump early SMP bring-up exceptions.

This will enable CPS debugging on more platforms and also
reduce code duplication.

All exception name strings are prefixed with CPS to help
identification with regular low-level interrupts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig.debug    | 52 +++++++++-------------------------------------
 arch/mips/kernel/Makefile  |  1 -
 arch/mips/kernel/cps-vec.S | 16 +++++++-------
 3 files changed, 18 insertions(+), 51 deletions(-)

diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 0ce6d24d05b3..caba00cd8a33 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -96,48 +96,6 @@ config SCACHE_DEBUGFS
 
 	  If unsure, say N.
 
-menuconfig MIPS_CPS_NS16550_BOOL
-	bool "CPS SMP NS16550 UART output"
-	depends on MIPS_CPS
-	help
-	  Output debug information via an ns16550 compatible UART if exceptions
-	  occur early in the boot process of a secondary core.
-
-if MIPS_CPS_NS16550_BOOL
-
-config MIPS_CPS_NS16550
-	def_bool MIPS_CPS_NS16550_BASE != 0
-
-config MIPS_CPS_NS16550_BASE
-	hex "UART Base Address"
-	default 0x1b0003f8 if MIPS_MALTA
-	default 0
-	help
-	  The base address of the ns16550 compatible UART on which to output
-	  debug information from the early stages of core startup.
-
-	  This is only used if non-zero.
-
-config MIPS_CPS_NS16550_SHIFT
-	int "UART Register Shift"
-	default 0
-	help
-	  The number of bits to shift ns16550 register indices by in order to
-	  form their addresses. That is, log base 2 of the span between
-	  adjacent ns16550 registers in the system.
-
-config MIPS_CPS_NS16550_WIDTH
-	int "UART Register Width"
-	default 1
-	help
-	  ns16550 registers width. UART registers IO access methods will be
-	  selected in accordance with this parameter. By setting it to 1, 2 or
-	  4 UART registers will be accessed by means of lb/sb, lh/sh or lw/sw
-	  instructions respectively. Any value not from that set activates
-	  lb/sb instructions.
-
-endif # MIPS_CPS_NS16550_BOOL
-
 # These options are only for real kernel hackers who want to get their hands dirty.
 config DEBUG_LL
 	bool "Kernel low-level debugging functions (read help!)"
@@ -320,3 +278,13 @@ config DEBUG_ZBOOT_EXCEPT
 	  during decompression of a compressed kernel via the DEBUG_LL output.
 
 	  If unsure, say N.
+
+config DEBUG_CPS_EXCEPT
+	bool "Enable kernel debugging of Coherent Processing System exceptions"
+	depends on MIPS_CPS && DEBUG_LL_EXCEPT
+	help
+	  Say Y here if you want to enable debugging of exceptions happen
+	  during SMP bring-up stages on processors witn MIPS Coherent Processing
+	  System support.
+
+	  If unsure, say N.
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 6641c3370e68..94325c02cae2 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -59,7 +59,6 @@ obj-$(CONFIG_MIPS_MT)		+= mips-mt.o
 obj-$(CONFIG_MIPS_MT_FPAFF)	+= mips-mt-fpaff.o
 obj-$(CONFIG_MIPS_MT_SMP)	+= smp-mt.o
 obj-$(CONFIG_MIPS_CPS)		+= smp-cps.o cps-vec.o
-obj-$(CONFIG_MIPS_CPS_NS16550)	+= cps-vec-ns16550.o
 obj-$(CONFIG_MIPS_SPRAM)	+= spram.o
 
 obj-$(CONFIG_MIPS_VPE_LOADER)	+= vpe.o
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index f876309130ad..49d682b3b49a 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -33,15 +33,15 @@
 # define STATUS_BITDEPS		0
 #endif
 
-#ifdef CONFIG_MIPS_CPS_NS16550
+#ifdef CONFIG_DEBUG_CPS_EXCEPT
 
 #define DUMP_EXCEP(name)		\
 	PTR_LA	a0, 8f;			\
-	jal	mips_cps_bev_dump;	\
+	jal	debug_ll_exception;	\
 	 nop;				\
 	TEXT(name)
 
-#else /* !CONFIG_MIPS_CPS_NS16550 */
+#else /* !CONFIG_DEBUG_CPS_EXCEPT */
 
 #define DUMP_EXCEP(name)
 
@@ -154,31 +154,31 @@ LEAF(mips_cps_core_boot)
 
 	__INIT
 LEAF(excep_tlbfill)
-	DUMP_EXCEP("TLB Fill")
+	DUMP_EXCEP("CPS - TLB Fill")
 	b	.
 	 nop
 	END(excep_tlbfill)
 
 LEAF(excep_xtlbfill)
-	DUMP_EXCEP("XTLB Fill")
+	DUMP_EXCEP("CPS - XTLB Fill")
 	b	.
 	 nop
 	END(excep_xtlbfill)
 
 LEAF(excep_cache)
-	DUMP_EXCEP("Cache")
+	DUMP_EXCEP("CPS - Cache")
 	b	.
 	 nop
 	END(excep_cache)
 
 LEAF(excep_genex)
-	DUMP_EXCEP("General")
+	DUMP_EXCEP("CPS - General")
 	b	.
 	 nop
 	END(excep_genex)
 
 LEAF(excep_intex)
-	DUMP_EXCEP("Interrupt")
+	DUMP_EXCEP("CPS - Interrupt")
 	b	.
 	 nop
 	END(excep_intex)

-- 
2.34.1