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From: Adrian Hunter <adrian.hunter@intel.com>
To: linux-kernel@vger.kernel.org
Cc: "Chang S. Bae" <chang.seok.bae@intel.com>,
	Masami Hiramatsu <mhiramat@kernel.org>,
	Nikolay Borisov <nik.borisov@suse.com>,
	Borislav Petkov <bp@alien8.de>,
	Ingo Molnar <mingo@redhat.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	x86@kernel.org,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Jiri Olsa <jolsa@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	linux-perf-users@vger.kernel.org
Subject: [PATCH 00/10] perf intel pt: Update instruction decoder for APX and other new instructions
Date: Thu,  2 May 2024 13:58:43 +0300
Message-Id: <20240502105853.5338-1-adrian.hunter@intel.com>
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Hi

The x86 instruction decoder is used not only for decoding kernel
instructions. It is also used by perf uprobes (user space probes) and by
perf tools Intel Processor Trace decoding. Consequently, it needs to
support instructions executed by user space also.

It should be noted that there are 2 copies of the instruction decoder.
One for the kernel and one for tools, which is a policy to prevent
changes from breaking builds.

Changes are based upon documents:

      Intel® Advanced Performance Extensions (Intel® APX)
      Architecture Specification
      April, 2024 Revision 4.0 355828-004

      Intel® Architecture Instruction Set Extensions
      and Future Features Programming Reference
      March 2024 319433-052

The patches depend on a patch by Chang S. Bae that they have already
submitted in their Key Locker patch set.  Nevertheless, the patch is
included in this patch set as well.

The final patch is an update to the perf tools' "x86 instruction decoder
test - new instructions" test, which provides testing.


Adrian Hunter (9):
      x86/insn: Fix PUSH instruction in x86 instruction decoder opcode map
      x86/insn: Add VEX versions of VPDPBUSD, VPDPBUSDS, VPDPWSSD and VPDPWSSDS
      x86/insn: Add misc new Intel instructions
      x86/insn: Add support for REX2 prefix to the instruction decoder logic
      x86/insn: x86/insn: Add support for REX2 prefix to the instruction decoder opcode map
      x86/insn: Add support for APX EVEX to the instruction decoder logic
      x86/insn: Add support for APX EVEX instructions to the opcode map
      perf intel pt: Add new JMPABS instruction to the Intel PT instruction decoder
      perf tests: Add APX and other new instructions to x86 instruction decoder test

Chang S. Bae (1):
      x86/insn: Add Key Locker instructions to the opcode map

 arch/x86/include/asm/inat.h                        |   17 +-
 arch/x86/include/asm/insn.h                        |   32 +-
 arch/x86/lib/insn.c                                |   29 +
 arch/x86/lib/x86-opcode-map.txt                    |  315 ++++--
 arch/x86/tools/gen-insn-attr-x86.awk               |   15 +-
 tools/arch/x86/include/asm/inat.h                  |   17 +-
 tools/arch/x86/include/asm/insn.h                  |   32 +-
 tools/arch/x86/lib/insn.c                          |   29 +
 tools/arch/x86/lib/x86-opcode-map.txt              |  315 ++++--
 tools/arch/x86/tools/gen-insn-attr-x86.awk         |   15 +-
 tools/perf/arch/x86/tests/insn-x86-dat-32.c        |  116 +++
 tools/perf/arch/x86/tests/insn-x86-dat-64.c        | 1026 ++++++++++++++++++++
 tools/perf/arch/x86/tests/insn-x86-dat-src.c       |  597 ++++++++++++
 .../util/intel-pt-decoder/intel-pt-insn-decoder.c  |    9 +
 14 files changed, 2370 insertions(+), 194 deletions(-)


Regards
Adrian