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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Greg Kroah-Hartman , Jiri Slaby , Robert Moore , Conor Dooley , Andrew Jones , Marc Zyngier , Atish Kumar Patra , Andrei Warkentin , Haibo1 Xu , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= Subject: Re: [PATCH v5 03/17] ACPI: bus: Add acpi_riscv_init function Message-ID: References: <20240501121742.1215792-1-sunilvl@ventanamicro.com> <20240501121742.1215792-4-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240501121742.1215792-4-sunilvl@ventanamicro.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo On Wed, May 01, 2024 at 05:47:28PM +0530, Sunil V L wrote: > Add a new function for RISC-V to do any architecture specific > initialization. This function will be used to create platform devices > like APLIC, PLIC, RISC-V IOMMU etc. This is similar to acpi_arm_init(). What is the special about this architecture that it requires a separate initialization that is _not_ going to be in other cases? Please, elaborate. -- With Best Regards, Andy Shevchenko