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Thu, 2 May 2024 07:34:05 -0700 From: Prajna Rajendra Kumar To: Mark Brown CC: Rob Herring , Krzysztof Kozlowski , , , , , Conor Dooley , Daire McNamara , , Prajna Rajendra Kumar Subject: [PATCH 0/3] Add support for GPIO based CS Date: Thu, 2 May 2024 15:34:07 +0100 Message-ID: <20240502143410.12629-1-prajna.rajendrakumar@microchip.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The Microchip PolarFire SoC SPI controller supports multiple chip selects. However, only one chip select is connected in the MSS. Therefore, use GPIO descriptors to configure additional chip select lines. Prajna Rajendra Kumar (3): spi: spi-microchip-core: Add support for GPIO based CS spi: dt-bindings: Add num-cs property for mpfs-spi spi: spi-microchip-core: Fix the number of chip selects supported .../bindings/spi/microchip,mpfs-spi.yaml | 19 ++++++++++++++++--- drivers/spi/spi-microchip-core.c | 6 +++++- 2 files changed, 21 insertions(+), 4 deletions(-) -- 2.25.1