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References: <20240502-cn9130-som-v4-0-0a2e2f1c70d8@solid-run.com> <20240502-cn9130-som-v4-4-0a2e2f1c70d8@solid-run.com>
In-Reply-To: <20240502-cn9130-som-v4-4-0a2e2f1c70d8@solid-run.com>
From: Rob Herring <robh@kernel.org>
Date: Thu, 2 May 2024 10:20:00 -0500
Message-ID: <CAL_JsqJGO9W5ysX_OWhP--8TGXiY19d5TeDL7Ne8rmj+GgWCcQ@mail.gmail.com>
Subject: Re: [PATCH v4 4/4] arm64: dts: add description for solidrun cn9131
 solidwan board
To: Josua Mayer <josua@solid-run.com>
Cc: Andrew Lunn <andrew@lunn.ch>, Gregory Clement <gregory.clement@bootlin.com>, 
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Yazan Shhady <yazan.shhady@solid-run.com>, linux-arm-kernel@lists.infradead.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
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On Thu, May 2, 2024 at 7:32=E2=80=AFAM Josua Mayer <josua@solid-run.com> wr=
ote:
>
> Add description for the SolidRun CN9131 SolidWAN, based on CN9130 SoM
> with an extra communication  processor on the carrier board.
>
> This board differentiates itself from CN9130 Clearfog by providing
> additional SoC native network interfaces and pci buses:
> 2x 10Gbps SFP+
> 4x 1Gbps RJ45
> 1x miniPCI-E
> 1x m.2 b-key with sata, usb-2.0 and usb-3.0
> 1x m.2 m-key with pcie and usb-2.0
> 1x m.2 b-key with pcie, usb-2.0, usb-3.0 and 2x sim slots
> 1x mpcie with pcie only
> 2x type-a usb-2.0/3.0
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
>  arch/arm64/boot/dts/marvell/Makefile               |   1 +
>  arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts | 643 +++++++++++++++=
++++++
>  2 files changed, 644 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/m=
arvell/Makefile
> index 019f2251d696..16f9d7156d9f 100644
> --- a/arch/arm64/boot/dts/marvell/Makefile
> +++ b/arch/arm64/boot/dts/marvell/Makefile
> @@ -30,3 +30,4 @@ dtb-$(CONFIG_ARCH_MVEBU) +=3D ac5x-rd-carrier-cn9131.dt=
b
>  dtb-$(CONFIG_ARCH_MVEBU) +=3D ac5-98dx35xx-rd.dtb
>  dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-cf-base.dtb
>  dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-cf-pro.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9131-cf-solidwan.dtb
> diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/ar=
m64/boot/dts/marvell/cn9131-cf-solidwan.dts
> new file mode 100644
> index 000000000000..a63a8961bad0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
> @@ -0,0 +1,643 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
> + *
> + * DTS for SolidRun CN9130 Clearfog Base.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/leds/common.h>
> +
> +#include "cn9130.dtsi"
> +#include "cn9130-sr-som.dtsi"
> +
> +/*
> + * Instantiate the external CP115
> + */
> +
> +#define CP11X_NAME             cp1
> +#define CP11X_BASE             f4000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE       f4600000
> +#define CP11X_PCIE1_BASE       f4620000
> +#define CP11X_PCIE2_BASE       f4640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +/ {
> +       model =3D "SolidRun CN9131 SolidWAN";
> +       compatible =3D "solidrun,cn9131-solidwan",
> +                    "solidrun,cn9130-sr-som", "marvell,cn9130";
> +
> +       aliases {
> +               ethernet0 =3D &cp1_eth1;
> +               ethernet1 =3D &cp1_eth2;
> +               ethernet2 =3D &cp0_eth1;
> +               ethernet3 =3D &cp0_eth2;
> +               ethernet4 =3D &cp0_eth0;
> +               ethernet5 =3D &cp1_eth0;
> +               gpio0 =3D &ap_gpio;
> +               gpio1 =3D &cp0_gpio1;
> +               gpio2 =3D &cp0_gpio2;
> +               gpio3 =3D &cp1_gpio1;
> +               gpio4 =3D &cp1_gpio2;
> +               gpio5 =3D &expander0;
> +               i2c0 =3D &cp0_i2c0;
> +               i2c1 =3D &cp0_i2c1;
> +               i2c2 =3D &cp1_i2c1;
> +               mmc0 =3D &ap_sdhci0;
> +               mmc1 =3D &cp0_sdhci0;
> +               rtc0 =3D &cp0_rtc;
> +               rtc1 =3D &carrier_rtc;
> +       };
> +
> +       leds {
> +               compatible =3D "gpio-leds";
> +               pinctrl-names =3D "default";
> +               pinctrl-0 =3D <&cp0_led_pins &cp1_led_pins>;
> +
> +               /* for sfp-1 (J42) */
> +               led-sfp1-activity {
> +                       label =3D "sfp1:green";
> +                       gpios =3D <&cp0_gpio1 7 GPIO_ACTIVE_HIGH>;
> +               };
> +
> +               /* for sfp-1 (J42) */
> +               led-sfp1-link {
> +                       label =3D "sfp1:yellow";
> +                       gpios =3D <&cp0_gpio1 4 GPIO_ACTIVE_HIGH>;
> +               };
> +
> +               /* (J28) */
> +               led-sfp0-activity {
> +                       label =3D "sfp0:green";
> +                       gpios =3D <&cp1_gpio2 22 GPIO_ACTIVE_HIGH>;
> +               };
> +
> +               /* (J28) */
> +               led-sfp0-link {
> +                       label =3D "sfp0:yellow";
> +                       gpios =3D <&cp1_gpio2 23 GPIO_ACTIVE_HIGH>;
> +               };
> +       };
> +
> +       /* Type-A port on J53 */
> +       reg_usb_a_vbus0: regulator-usb-a-vbus0 {
> +               compatible =3D "regulator-fixed";
> +               pinctrl-0 =3D <&cp0_reg_usb_a_vbus0_pins>;
> +               pinctrl-names =3D "default";
> +               regulator-name =3D "vbus0";
> +               regulator-min-microvolt =3D <5000000>;
> +               regulator-max-microvolt =3D <5000000>;
> +               regulator-oc-protection-microamp =3D <1000000>;
> +               gpio =3D <&cp0_gpio1 27 GPIO_ACTIVE_HIGH>;

"gpio" is deprecated.

> +               enable-active-high;
> +               regulator-always-on;
> +       };
> +
> +       reg_usb_a_vbus1: regulator-usb-a-vbus1 {
> +               compatible =3D "regulator-fixed";
> +               pinctrl-0 =3D <&cp0_reg_usb_a_vbus1_pins>;
> +               pinctrl-names =3D "default";
> +               regulator-name =3D "vbus1";
> +               regulator-min-microvolt =3D <5000000>;
> +               regulator-max-microvolt =3D <5000000>;
> +               regulator-oc-protection-microamp =3D <1000000>;
> +               gpio =3D <&cp0_gpio1 28 GPIO_ACTIVE_HIGH>;
> +               enable-active-high;
> +               regulator-always-on;
> +       };
> +
> +       sfp0: sfp-0 {
> +               compatible =3D "sff,sfp";
> +               pinctrl-0 =3D <&cp0_sfp0_pins>;
> +               pinctrl-names =3D "default";
> +               i2c-bus =3D <&cp0_i2c1>;
> +               los-gpio =3D <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>;
> +               mod-def0-gpio =3D <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
> +               tx-disable-gpio =3D <&cp0_gpio2 1 GPIO_ACTIVE_HIGH>;
> +               tx-fault-gpio =3D <&cp0_gpio1 31 GPIO_ACTIVE_HIGH>;

As is "-gpio" suffix.  These are all pointed out with 'dtbs_check'
which I sent a report on v3. I haven't checked what else from that you
ignored... I don't expect warnings inherited from the SoC .dtsi to be
fixed in this series, but certainly the board level ones. Yes, it's
hard to pick out those, but that's the Marvell folks fault for not
fixing SoC level warnings.

Rob