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From: Peng Fan <peng.fan@nxp.com>
To: Frank Li <frank.li@nxp.com>, "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
CC: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha
 Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team
	<kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"imx@lists.linux.dev" <imx@lists.linux.dev>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>, Alexander Stein
	<alexander.stein@ew.tq-group.com>
Subject: RE: [PATCH v4 2/3] arm64: dts: freescale: add i.MX95 basic dtsi
Thread-Topic: [PATCH v4 2/3] arm64: dts: freescale: add i.MX95 basic dtsi
Thread-Index: AQHanPlY38GlXhK1oUSQ9eqcWXlvlbGE13GAgAACDEA=
Date: Fri, 3 May 2024 03:27:51 +0000
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> Subject: Re: [PATCH v4 2/3] arm64: dts: freescale: add i.MX95 basic dtsi
>=20
> On Fri, May 03, 2024 at 09:37:12AM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > i.MX95 features 6 A55 Cores, ARM Mali GPU, ISP, ML acceleration NPU,
> > and Edgelock secure enclave security. This patch is to add a minimal
> > dtsi, with cpu cores, coresight, scmi, gic, uart, mu, sdhc, lpi2c added=
.
> >

...
> > +	};
> > +
> > +	sram1: sram@20480000 {
> > +		compatible =3D "mmio-sram";
> > +		reg =3D <0x0 0x204c0000 0x0 0x18000>;
> > +		ranges =3D <0x0 0x0 0x204c0000 0x18000>;
> > +		#address-cells =3D <1>;
> > +		#size-cells =3D <1>;
> > +	};
>=20
> looks like it need general node name in
> https://github.com/devicetree-org/devicetree-
> specification/releases/download/v0.4/devicetree-specification-v0.4.pdf
> section 2.2.2
>=20
> look like should be "sram-controller", please also check other node name =
to
> match spec.

But this is not controller, it is just a piece of on chip memory.

Thanks,
Peng.
>=20
> Frank
>=20
> > +
> > +	firmware {
> > +		scmi {
> > +			compatible =3D "arm,scmi";
> > +			mboxes =3D <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>;
> > +			shmem =3D <&scmi_buf0>, <&scmi_buf1>;
> > +			#address-cells =3D <1>;
> > +			#size-cells =3D <0>;
> > +
> > +			scmi_devpd: protocol@11 {
> > +				reg =3D <0x11>;
> > +				#power-domain-cells =3D <1>;
> > +			};
> > +
> > +			scmi_perf: protocol@13 {
> > +				reg =3D <0x13>;
> > +				#power-domain-cells =3D <1>;
> > +			};
> > +
> > +			scmi_clk: protocol@14 {
> > +				reg =3D <0x14>;
> > +				#clock-cells =3D <1>;
> > +			};
> > +
> > +			scmi_sensor: protocol@15 {
> > +				reg =3D <0x15>;
> > +				#thermal-sensor-cells =3D <1>;
> > +			};
> > +		};
> > +	};
> > +
> > +	pmu {
> > +		compatible =3D "arm,cortex-a55-pmu";
> > +		interrupts =3D <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_HIGH)>;
> > +	};
> > +
> > +	thermal-zones {
> > +		a55-thermal {
> > +			polling-delay-passive =3D <250>;
> > +			polling-delay =3D <2000>;
> > +			thermal-sensors =3D <&scmi_sensor 1>;
> > +
> > +			trips {
> > +				cpu_alert0: trip0 {
> > +					temperature =3D <85000>;
> > +					hysteresis =3D <2000>;
> > +					type =3D "passive";
> > +				};
> > +
> > +				cpu_crit0: trip1 {
> > +					temperature =3D <95000>;
> > +					hysteresis =3D <2000>;
> > +					type =3D "critical";
> > +				};
> > +			};
> > +
> > +			cooling-maps {
> > +				map0 {
> > +					trip =3D <&cpu_alert0>;
> > +					cooling-device =3D
> > +						<&A55_0
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > +						<&A55_1
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > +						<&A55_2
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > +						<&A55_3
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > +						<&A55_4
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > +						<&A55_5
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > +				};
> > +			};
> > +		};
> > +	};
> > +
> > +	psci {
> > +		compatible =3D "arm,psci-1.0";
> > +		method =3D "smc";
> > +	};
> > +
> > +	timer {
> > +		compatible =3D "arm,armv8-timer";
> > +		interrupts =3D <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>;
> > +		clock-frequency =3D <24000000>;
> > +		arm,no-tick-in-suspend;
> > +		interrupt-parent =3D <&gic>;
> > +	};
> > +
> > +	gic: interrupt-controller@48000000 {
> > +		compatible =3D "arm,gic-v3";
> > +		reg =3D <0 0x48000000 0 0x10000>,
> > +		      <0 0x48060000 0 0xc0000>;
> > +		#address-cells =3D <2>;
> > +		#size-cells =3D <2>;
> > +		#interrupt-cells =3D <3>;
> > +		interrupt-controller;
> > +		interrupts =3D <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-parent =3D <&gic>;
> > +		dma-noncoherent;
> > +		ranges;
> > +
> > +		its: msi-controller@48040000 {
> > +			compatible =3D "arm,gic-v3-its";
> > +			reg =3D <0 0x48040000 0 0x20000>;
> > +			msi-controller;
> > +			#msi-cells =3D <1>;
> > +			dma-noncoherent;
> > +		};
> > +	};
> > +
> > +	soc {
> > +		compatible =3D "simple-bus";
> > +		#address-cells =3D <2>;
> > +		#size-cells =3D <2>;
> > +		ranges;
> > +
> > +		aips2: bus@42000000 {
> > +			compatible =3D "fsl,aips-bus", "simple-bus";
> > +			reg =3D <0x0 0x42000000 0x0 0x800000>;
> > +			ranges =3D <0x42000000 0x0 0x42000000
> 0x8000000>,
> > +				 <0x28000000 0x0 0x28000000
> 0x10000000>;
> > +			#address-cells =3D <1>;
> > +			#size-cells =3D <1>;
> > +
> > +			mu7: mailbox@42430000 {
> > +				compatible =3D "fsl,imx95-mu";
> > +				reg =3D <0x42430000 0x10000>;
> > +				interrupts =3D <GIC_SPI 234
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				#mbox-cells =3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			wdog3: watchdog@42490000 {
> > +				compatible =3D "fsl,imx93-wdt";
> > +				reg =3D <0x42490000 0x10000>;
> > +				interrupts =3D <GIC_SPI 77
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				timeout-sec =3D <40>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			tpm3: pwm@424e0000 {
> > +				compatible =3D "fsl,imx7ulp-pwm";
> > +				reg =3D <0x424e0000 0x1000>;
> > +				clocks =3D <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				#pwm-cells =3D <3>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			tpm4: pwm@424f0000 {
> > +				compatible =3D "fsl,imx7ulp-pwm";
> > +				reg =3D <0x424f0000 0x1000>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_TPM4>;
> > +				#pwm-cells =3D <3>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			tpm5: pwm@42500000 {
> > +				compatible =3D "fsl,imx7ulp-pwm";
> > +				reg =3D <0x42500000 0x1000>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_TPM5>;
> > +				#pwm-cells =3D <3>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			tpm6: pwm@42510000 {
> > +				compatible =3D "fsl,imx7ulp-pwm";
> > +				reg =3D <0x42510000 0x1000>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_TPM6>;
> > +				#pwm-cells =3D <3>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpi2c3: i2c@42530000 {
> > +				compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-
> lpi2c";
> > +				reg =3D <0x42530000 0x10000>;
> > +				interrupts =3D <GIC_SPI 58
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPI2C3>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpi2c4: i2c@42540000 {
> > +				compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-
> lpi2c";
> > +				reg =3D <0x42540000 0x10000>;
> > +				interrupts =3D <GIC_SPI 59
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPI2C4>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpspi3: spi@42550000 {
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <0>;
> > +				compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-
> spi";
> > +				reg =3D <0x42550000 0x10000>;
> > +				interrupts =3D <GIC_SPI 61
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPSPI3>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpspi4: spi@42560000 {
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <0>;
> > +				compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-
> spi";
> > +				reg =3D <0x42560000 0x10000>;
> > +				interrupts =3D <GIC_SPI 62
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPSPI4>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart3: serial@42570000 {
> > +				compatible =3D "fsl,imx95-lpuart",
> "fsl,imx8ulp-lpuart",
> > +					     "fsl,imx7ulp-lpuart";
> > +				reg =3D <0x42570000 0x1000>;
> > +				interrupts =3D <GIC_SPI 64
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPUART3>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart4: serial@42580000 {
> > +				compatible =3D "fsl,imx95-lpuart",
> "fsl,imx8ulp-lpuart",
> > +					     "fsl,imx7ulp-lpuart";
> > +				reg =3D <0x42580000 0x1000>;
> > +				interrupts =3D <GIC_SPI 65
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPUART4>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart5: serial@42590000 {
> > +				compatible =3D "fsl,imx95-lpuart",
> "fsl,imx8ulp-lpuart",
> > +					     "fsl,imx7ulp-lpuart";
> > +				reg =3D <0x42590000 0x1000>;
> > +				interrupts =3D <GIC_SPI 66
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPUART5>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart6: serial@425a0000 {
> > +				compatible =3D "fsl,imx95-lpuart",
> "fsl,imx8ulp-lpuart",
> > +					     "fsl,imx7ulp-lpuart";
> > +				reg =3D <0x425a0000 0x1000>;
> > +				interrupts =3D <GIC_SPI 67
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPUART6>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart7: serial@42690000 {
> > +				compatible =3D "fsl,imx95-lpuart",
> "fsl,imx8ulp-lpuart",
> > +					     "fsl,imx7ulp-lpuart";
> > +				reg =3D <0x42690000 0x1000>;
> > +				interrupts =3D <GIC_SPI 68
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPUART7>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart8: serial@426a0000 {
> > +				compatible =3D "fsl,imx95-lpuart",
> "fsl,imx8ulp-lpuart",
> > +					     "fsl,imx7ulp-lpuart";
> > +				reg =3D <0x426a0000 0x1000>;
> > +				interrupts =3D <GIC_SPI 69
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPUART8>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpi2c5: i2c@426b0000 {
> > +				compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-
> lpi2c";
> > +				reg =3D <0x426b0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 181
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPI2C5>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpi2c6: i2c@426c0000 {
> > +				compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-
> lpi2c";
> > +				reg =3D <0x426c0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 182
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPI2C6>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpi2c7: i2c@426d0000 {
> > +				compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-
> lpi2c";
> > +				reg =3D <0x426d0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 183
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPI2C7>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpi2c8: i2c@426e0000 {
> > +				compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-
> lpi2c";
> > +				reg =3D <0x426e0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 184
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPI2C8>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpspi5: spi@426f0000 {
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <0>;
> > +				compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-
> spi";
> > +				reg =3D <0x426f0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 177
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPSPI5>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpspi6: spi@42700000 {
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <0>;
> > +				compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-
> spi";
> > +				reg =3D <0x42700000 0x10000>;
> > +				interrupts =3D <GIC_SPI 178
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPSPI6>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpspi7: spi@42710000 {
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <0>;
> > +				compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-
> spi";
> > +				reg =3D <0x42710000 0x10000>;
> > +				interrupts =3D <GIC_SPI 179
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPSPI7>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpspi8: spi@42720000 {
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <0>;
> > +				compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-
> spi";
> > +				reg =3D <0x42720000 0x10000>;
> > +				interrupts =3D <GIC_SPI 180
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPSPI8>,
> > +					 <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			mu8: mailbox@42730000 {
> > +				compatible =3D "fsl,imx95-mu";
> > +				reg =3D <0x42730000 0x10000>;
> > +				interrupts =3D <GIC_SPI 235
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk
> IMX95_CLK_BUSWAKEUP>;
> > +				#mbox-cells =3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +		};
> > +
> > +		aips3: bus@42800000 {
> > +			compatible =3D "fsl,aips-bus", "simple-bus";
> > +			reg =3D <0 0x42800000 0 0x800000>;
> > +			#address-cells =3D <1>;
> > +			#size-cells =3D <1>;
> > +			ranges =3D <0x42800000 0x0 0x42800000 0x800000>;
> > +
> > +			usdhc1: mmc@42850000 {
> > +				compatible =3D "fsl,imx95-usdhc",
> "fsl,imx8mm-usdhc";
> > +				reg =3D <0x42850000 0x10000>;
> > +				interrupts =3D <GIC_SPI 86
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk
> IMX95_CLK_BUSWAKEUP>,
> > +					 <&scmi_clk
> IMX95_CLK_WAKEUPAXI>,
> > +					 <&scmi_clk IMX95_CLK_USDHC1>;
> > +				clock-names =3D "ipg", "ahb", "per";
> > +				assigned-clocks =3D <&scmi_clk
> IMX95_CLK_USDHC1>;
> > +				assigned-clock-parents =3D <&scmi_clk
> IMX95_CLK_SYSPLL1_PFD1>;
> > +				assigned-clock-rates =3D <400000000>;
> > +				bus-width =3D <8>;
> > +				fsl,tuning-start-tap =3D <1>;
> > +				fsl,tuning-step=3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			usdhc2: mmc@42860000 {
> > +				compatible =3D "fsl,imx95-usdhc",
> "fsl,imx8mm-usdhc";
> > +				reg =3D <0x42860000 0x10000>;
> > +				interrupts =3D <GIC_SPI 87
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk
> IMX95_CLK_BUSWAKEUP>,
> > +					 <&scmi_clk
> IMX95_CLK_WAKEUPAXI>,
> > +					 <&scmi_clk IMX95_CLK_USDHC2>;
> > +				clock-names =3D "ipg", "ahb", "per";
> > +				assigned-clocks =3D <&scmi_clk
> IMX95_CLK_USDHC2>;
> > +				assigned-clock-parents =3D <&scmi_clk
> IMX95_CLK_SYSPLL1_PFD1>;
> > +				assigned-clock-rates =3D <400000000>;
> > +				bus-width =3D <4>;
> > +				fsl,tuning-start-tap =3D <1>;
> > +				fsl,tuning-step=3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			usdhc3: mmc@428b0000 {
> > +				compatible =3D "fsl,imx95-usdhc",
> "fsl,imx8mm-usdhc";
> > +				reg =3D <0x428b0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 191
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk
> IMX95_CLK_BUSWAKEUP>,
> > +					 <&scmi_clk
> IMX95_CLK_WAKEUPAXI>,
> > +					 <&scmi_clk IMX95_CLK_USDHC3>;
> > +				clock-names =3D "ipg", "ahb", "per";
> > +				assigned-clock-parents =3D <&scmi_clk
> IMX95_CLK_SYSPLL1_PFD1>;
> > +				assigned-clock-rates =3D <400000000>;
> > +				bus-width =3D <4>;
> > +				fsl,tuning-start-tap =3D <1>;
> > +				fsl,tuning-step=3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +		};
> > +
> > +		gpio2: gpio@43810000 {
> > +			compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> > +			reg =3D <0x0 0x43810000 0x0 0x1000>;
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> > +				 <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> > +			clock-names =3D "gpio", "port";
> > +		};
> > +
> > +		gpio3: gpio@43820000 {
> > +			compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> > +			reg =3D <0x0 0x43820000 0x0 0x1000>;
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> > +				 <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> > +			clock-names =3D "gpio", "port";
> > +		};
> > +
> > +		gpio4: gpio@43840000 {
> > +			compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> > +			reg =3D <0x0 0x43840000 0x0 0x1000>;
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> > +				 <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> > +			clock-names =3D "gpio", "port";
> > +		};
> > +
> > +		gpio5: gpio@43850000 {
> > +			compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> > +			reg =3D <0x0 0x43850000 0x0 0x1000>;
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>,
> > +				 <&scmi_clk IMX95_CLK_BUSWAKEUP>;
> > +			clock-names =3D "gpio", "port";
> > +		};
> > +
> > +		aips1: bus@44000000 {
> > +			compatible =3D "fsl,aips-bus", "simple-bus";
> > +			reg =3D <0x0 0x44000000 0x0 0x800000>;
> > +			ranges =3D <0x44000000 0x0 0x44000000 0x800000>;
> > +			#address-cells =3D <1>;
> > +			#size-cells =3D <1>;
> > +
> > +			mu1: mailbox@44220000 {
> > +				compatible =3D "fsl,imx95-mu";
> > +				reg =3D <0x44220000 0x10000>;
> > +				interrupts =3D <GIC_SPI 224
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_BUSAON>;
> > +				#mbox-cells =3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			tpm1: pwm@44310000 {
> > +				compatible =3D "fsl,imx7ulp-pwm";
> > +				reg =3D <0x44310000 0x1000>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_BUSAON>;
> > +				#pwm-cells =3D <3>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			tpm2: pwm@44320000 {
> > +				compatible =3D "fsl,imx7ulp-pwm";
> > +				reg =3D <0x44320000 0x1000>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_TPM2>;
> > +				#pwm-cells =3D <3>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpi2c1: i2c@44340000 {
> > +				compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-
> lpi2c";
> > +				reg =3D <0x44340000 0x10000>;
> > +				interrupts =3D <GIC_SPI 13
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPI2C1>,
> > +					 <&scmi_clk IMX95_CLK_BUSAON>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpi2c2: i2c@44350000 {
> > +				compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-
> lpi2c";
> > +				reg =3D <0x44350000 0x10000>;
> > +				interrupts =3D <GIC_SPI 14
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPI2C2>,
> > +					 <&scmi_clk IMX95_CLK_BUSAON>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpspi1: spi@44360000 {
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <0>;
> > +				compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-
> spi";
> > +				reg =3D <0x44360000 0x10000>;
> > +				interrupts =3D <GIC_SPI 16
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPSPI1>,
> > +					 <&scmi_clk IMX95_CLK_BUSAON>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpspi2: spi@44370000 {
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <0>;
> > +				compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-
> spi";
> > +				reg =3D <0x44370000 0x10000>;
> > +				interrupts =3D <GIC_SPI 17
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPSPI2>,
> > +					 <&scmi_clk IMX95_CLK_BUSAON>;
> > +				clock-names =3D "per", "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart1: serial@44380000 {
> > +				compatible =3D "fsl,imx95-lpuart",
> "fsl,imx8ulp-lpuart",
> > +					     "fsl,imx7ulp-lpuart";
> > +				reg =3D <0x44380000 0x1000>;
> > +				interrupts =3D <GIC_SPI 19
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPUART1>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			lpuart2: serial@44390000 {
> > +				compatible =3D "fsl,imx95-lpuart",
> "fsl,imx8ulp-lpuart",
> > +					     "fsl,imx7ulp-lpuart";
> > +				reg =3D <0x44390000 0x1000>;
> > +				interrupts =3D <GIC_SPI 20
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_LPUART2>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			adc1: adc@44530000 {
> > +				compatible =3D "nxp,imx93-adc";
> > +				reg =3D <0x44530000 0x10000>;
> > +				interrupts =3D <GIC_SPI 199
> IRQ_TYPE_LEVEL_HIGH>,
> > +					     <GIC_SPI 200
> IRQ_TYPE_LEVEL_HIGH>,
> > +					     <GIC_SPI 201
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_ADC>;
> > +				clock-names =3D "ipg";
> > +				status =3D "disabled";
> > +			};
> > +
> > +			mu2: mailbox@445b0000 {
> > +				compatible =3D "fsl,imx95-mu";
> > +				reg =3D <0x445b0000 0x1000>;
> > +				ranges;
> > +				interrupts =3D <GIC_SPI 226
> IRQ_TYPE_LEVEL_HIGH>;
> > +				#address-cells =3D <1>;
> > +				#size-cells =3D <1>;
> > +				#mbox-cells =3D <2>;
> > +
> > +				sram0: sram@445b1000 {
> > +					compatible =3D "mmio-sram";
> > +					reg =3D <0x445b1000 0x400>;
> > +					ranges =3D <0x0 0x445b1000 0x400>;
> > +					#address-cells =3D <1>;
> > +					#size-cells =3D <1>;
> > +
> > +					scmi_buf0: scmi-sram-section@0 {
> > +						compatible =3D "arm,scmi-
> shmem";
> > +						reg =3D <0x0 0x80>;
> > +					};
> > +
> > +					scmi_buf1: scmi-sram-section@80
> {
> > +						compatible =3D "arm,scmi-
> shmem";
> > +						reg =3D <0x80 0x80>;
> > +					};
> > +				};
> > +
> > +			};
> > +
> > +			mu3: mailbox@445d0000 {
> > +				compatible =3D "fsl,imx95-mu";
> > +				reg =3D <0x445d0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 228
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_BUSAON>;
> > +				#mbox-cells =3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			mu4: mailbox@445f0000 {
> > +				compatible =3D "fsl,imx95-mu";
> > +				reg =3D <0x445f0000 0x10000>;
> > +				interrupts =3D <GIC_SPI 230
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_BUSAON>;
> > +				#mbox-cells =3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +
> > +			mu6: mailbox@44630000 {
> > +				compatible =3D "fsl,imx95-mu";
> > +				reg =3D <0x44630000 0x10000>;
> > +				interrupts =3D <GIC_SPI 206
> IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks =3D <&scmi_clk IMX95_CLK_BUSAON>;
> > +				#mbox-cells =3D <2>;
> > +				status =3D "disabled";
> > +			};
> > +		};
> > +
> > +		mailbox@47320000 {
> > +			compatible =3D "fsl,imx95-mu-v2x";
> > +			reg =3D <0x0 0x47320000 0x0 0x10000>;
> > +			interrupts =3D <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
> > +			#mbox-cells =3D <2>;
> > +		};
> > +
> > +		mailbox@47350000 {
> > +			compatible =3D "fsl,imx95-mu-v2x";
> > +			reg =3D <0x0 0x47350000 0x0 0x10000>;
> > +			interrupts =3D <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
> > +			#mbox-cells =3D <2>;
> > +		};
> > +
> > +		/* GPIO1 is under exclusive control of System Manager */
> > +		gpio1: gpio@47400000 {
> > +			compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
> > +			reg =3D <0x0 0x47400000 0x0 0x1000>;
> > +			gpio-controller;
> > +			#gpio-cells =3D <2>;
> > +			interrupts =3D <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells =3D <2>;
> > +			clocks =3D <&scmi_clk IMX95_CLK_M33>,
> > +				 <&scmi_clk IMX95_CLK_M33>;
> > +			clock-names =3D "gpio", "port";
> > +			status =3D "disabled";
> > +		};
> > +
> > +		elemu0: mailbox@47520000 {
> > +			compatible =3D "fsl,imx95-mu-ele";
> > +			reg =3D <0x0 0x47520000 0x0 0x10000>;
> > +			interrupts =3D <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > +			#mbox-cells =3D <2>;
> > +			status =3D "disabled";
> > +		};
> > +
> > +		elemu1: mailbox@47530000 {
> > +			compatible =3D "fsl,imx95-mu-ele";
> > +			reg =3D <0x0 0x47530000 0x0 0x10000>;
> > +			interrupts =3D <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> > +			#mbox-cells =3D <2>;
> > +			status =3D "disabled";
> > +		};
> > +
> > +		elemu2: mailbox@47540000 {
> > +			compatible =3D "fsl,imx95-mu-ele";
> > +			reg =3D <0x0 0x47540000 0x0 0x10000>;
> > +			interrupts =3D <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> > +			#mbox-cells =3D <2>;
> > +			status =3D "disabled";
> > +		};
> > +
> > +		elemu3: mailbox@47550000 {
> > +			compatible =3D "fsl,imx95-mu-ele";
> > +			reg =3D <0x0 0x47550000 0x0 0x10000>;
> > +			interrupts =3D <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> > +			#mbox-cells =3D <2>;
> > +		};
> > +
> > +		elemu4: mailbox@47560000 {
> > +			compatible =3D "fsl,imx95-mu-ele";
> > +			reg =3D <0x0 0x47560000 0x0 0x10000>;
> > +			interrupts =3D <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> > +			#mbox-cells =3D <2>;
> > +			status =3D "disabled";
> > +		};
> > +
> > +		elemu5: mailbox@47570000 {
> > +			compatible =3D "fsl,imx95-mu-ele";
> > +			reg =3D <0x0 0x47570000 0x0 0x10000>;
> > +			interrupts =3D <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> > +			#mbox-cells =3D <2>;
> > +			status =3D "disabled";
> > +		};
> > +
> > +		aips4: bus@49000000 {
> > +			compatible =3D "fsl,aips-bus", "simple-bus";
> > +			reg =3D <0x0 0x49000000 0x0 0x800000>;
> > +			ranges =3D <0x49000000 0x0 0x49000000 0x800000>;
> > +			#address-cells =3D <1>;
> > +			#size-cells =3D <1>;
> > +
> > +			smmu: iommu@490d0000 {
> > +				compatible =3D "arm,smmu-v3";
> > +				reg =3D <0x490d0000 0x100000>;
> > +				interrupts =3D <GIC_SPI 325
> IRQ_TYPE_EDGE_RISING>,
> > +					     <GIC_SPI 328
> IRQ_TYPE_EDGE_RISING>,
> > +					     <GIC_SPI 334
> IRQ_TYPE_EDGE_RISING>,
> > +					     <GIC_SPI 326
> IRQ_TYPE_EDGE_RISING>;
> > +				interrupt-names =3D "eventq", "gerror", "priq",
> "cmdq-sync";
> > +				#iommu-cells =3D <1>;
> > +				status =3D "disabled";
> > +			};
> > +		};
> > +	};
> > +};
> >
> > --
> > 2.37.1
> >