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02 May 2024 22:38:16 -0700 Received: from kbuild by e434dd42e5a1 with local (Exim 4.96) (envelope-from ) id 1s2lcb-000BLu-1O; Fri, 03 May 2024 05:38:13 +0000 Date: Fri, 3 May 2024 13:37:50 +0800 From: kernel test robot To: Prajna Rajendra Kumar , Mark Brown Cc: oe-kbuild-all@lists.linux.dev, Rob Herring , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Conor Dooley , Daire McNamara , valentina.fernandezalanis@microchip.com, Prajna Rajendra Kumar Subject: Re: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based CS Message-ID: <202405031322.8UuTAWrf-lkp@intel.com> References: <20240502143410.12629-2-prajna.rajendrakumar@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240502143410.12629-2-prajna.rajendrakumar@microchip.com> Hi Prajna, kernel test robot noticed the following build warnings: [auto build test WARNING on broonie-spi/for-next] [also build test WARNING on robh/for-next krzk-dt/for-next linus/master v6.9-rc6 next-20240502] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Prajna-Rajendra-Kumar/spi-spi-microchip-core-Add-support-for-GPIO-based-CS/20240502-223714 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next patch link: https://lore.kernel.org/r/20240502143410.12629-2-prajna.rajendrakumar%40microchip.com patch subject: [PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based CS config: sh-allmodconfig (https://download.01.org/0day-ci/archive/20240503/202405031322.8UuTAWrf-lkp@intel.com/config) compiler: sh4-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240503/202405031322.8UuTAWrf-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202405031322.8UuTAWrf-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/spi/spi-microchip-core.c: In function 'mchp_corespi_setup': >> drivers/spi/spi-microchip-core.c:261:13: warning: the comparison will always evaluate as 'true' for the address of 'cs_gpiod' will never be NULL [-Waddress] 261 | if (spi->cs_gpiod) | ^~~ In file included from drivers/spi/spi-microchip-core.c:21: include/linux/spi/spi.h:219:34: note: 'cs_gpiod' declared here 219 | struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */ | ^~~~~~~~ vim +261 drivers/spi/spi-microchip-core.c 255 256 static int mchp_corespi_setup(struct spi_device *spi) 257 { 258 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); 259 u32 reg; 260 > 261 if (spi->cs_gpiod) 262 return 0; 263 264 /* 265 * Active high targets need to be specifically set to their inactive 266 * states during probe by adding them to the "control group" & thus 267 * driving their select line low. 268 */ 269 if (spi->mode & SPI_CS_HIGH) { 270 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT); 271 reg |= BIT(spi_get_chipselect(spi, 0)); 272 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg); 273 } 274 return 0; 275 } 276 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki