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From: "Boddu, Sai Pavan" <sai.pavan.boddu@amd.com>
To: Andi Shyti <andi.shyti@kernel.org>
CC: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-i2c@vger.kernel.org" <linux-i2c@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>, "Simek, Michal"
	<michal.simek@amd.com>, Lars-Peter Clausen <lars@metafoo.de>, Wolfram Sang
	<wsa@kernel.org>
Subject: RE: [PATCH] i2c: cadence: Avoid fifo clear after start
Thread-Topic: [PATCH] i2c: cadence: Avoid fifo clear after start
Thread-Index: AQHaSUfcsQJjTnMwH0iIfDUOatck5LDeSs0AgAA0hYCApibR8A==
Date: Fri, 3 May 2024 09:05:37 +0000
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Hi Andi,

Sorry, I did not close on this one.
Anyway I will re-spin fixing the commit message issues. More comments inlin=
e below.

>-----Original Message-----
>From: Andi Shyti <andi.shyti@kernel.org>
>Sent: Thursday, January 18, 2024 2:36 AM
>To: Boddu, Sai Pavan <sai.pavan.boddu@amd.com>
>Cc: linux-kernel@vger.kernel.org; linux-i2c@vger.kernel.org; linux-arm-
>kernel@lists.infradead.org; Simek, Michal <michal.simek@amd.com>; Lars-
>Peter Clausen <lars@metafoo.de>; Wolfram Sang <wsa@kernel.org>
>Subject: Re: [PATCH] i2c: cadence: Avoid fifo clear after start
>
>Hi,
>
>> >> b/drivers/i2c/busses/i2c-cadence.c
>> >> index de3f58b60dce..6f7d753a8197 100644
>> >> --- a/drivers/i2c/busses/i2c-cadence.c
>> >> +++ b/drivers/i2c/busses/i2c-cadence.c
>> >> @@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
>> >>
>> >>  	if (hold_clear) {
>> >>  		ctrl_reg &=3D ~CDNS_I2C_CR_HOLD;
>> >> +		ctrl_reg &=3D ~CDNS_I2C_CR_CLR_FIFO;
>> >
>> >I'm wondering whether the whole ctrl_reg should be reset after the firs=
t
>write.
>
>> [Boddu, Sai Pavan] previous implementation of read-modify-write was good
>then ?
>
>I don't know, I'm just asking... because rather than read-modify-write, th=
is is
>read-modify-write-modify-write :-)
>
>I'm just wondering if after the first write ctrl_reg is still holding a va=
lid value.
[Boddu, Sai Pavan] Yes, all bits in ctrl_reg stay as configured except CLR_=
FIFO which is self-clearing.
None of the other bits would change state.

CLR_FIFO post start of transactions should not be allowed; this patch addre=
ss the same.

Regards,
Sai Pavan=20
>
>Andi