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From: Jian-Hong Pan <jhp@endlessos.org>
Date: Fri, 3 May 2024 17:45:49 +0800
Message-ID: <CAPpJ_efYWWxGBopbSQHB=Y2+1RrXFR2XWeqEhGTgdiw3XX0Jmw@mail.gmail.com>
Subject: Re: [PATCH v5 4/4] PCI/ASPM: Fix L1.2 parameters when enable link state
To: david.e.box@linux.intel.com
Cc: Bjorn Helgaas <helgaas@kernel.org>, Johan Hovold <johan@kernel.org>, 
	=?UTF-8?Q?Ilpo_J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>, 
	Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>, 
	Mika Westerberg <mika.westerberg@linux.intel.com>, Damien Le Moal <dlemoal@kernel.org>, 
	Nirmal Patel <nirmal.patel@linux.intel.com>, 
	Jonathan Derrick <jonathan.derrick@linux.dev>, linux-pci@vger.kernel.org, 
	linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
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David E. Box <david.e.box@linux.intel.com> =E6=96=BC 2024=E5=B9=B45=E6=9C=
=881=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8A=E5=8D=882:26=E5=AF=AB=E9=81=93=
=EF=BC=9A
>
> On Tue, 2024-04-30 at 15:46 +0800, Jian-Hong Pan wrote:
> > David E. Box <david.e.box@linux.intel.com> =E6=96=BC 2024=E5=B9=B44=E6=
=9C=8827=E6=97=A5 =E9=80=B1=E5=85=AD =E4=B8=8A=E5=8D=888:03=E5=AF=AB=E9=81=
=93=EF=BC=9A
> > >
> > > Hi Jian-Hong,
> > >
> > > On Wed, 2024-04-24 at 19:02 +0800, Jian-Hong Pan wrote:
> > > > Currently, when enable link's L1.2 features with
> > > > __pci_enable_link_state(),
> > > > it configs the link directly without ensuring related L1.2 paramete=
rs,
> > > > such
> > > > as T_POWER_ON, Common_Mode_Restore_Time, and LTR_L1.2_THRESHOLD hav=
e been
> > > > programmed.
> > > >
> > > > This leads the link's L1.2 between PCIe Root Port and child device =
gets
> > > > wrong configs when a caller tries to enabled it.
> > > >
> > > > Here is a failed example on ASUS B1400CEAE with enabled VMD:
> > > >
> > > > 10000:e0:06.0 PCI bridge: Intel Corporation 11th Gen Core Processor=
 PCIe
> > > > Controller (rev 01) (prog-if 00 [Normal decode])
> > > >     ...
> > > >     Capabilities: [200 v1] L1 PM Substates
> > > >         L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
> > > > L1_PM_Substates+
> > > >                   PortCommonModeRestoreTime=3D45us PortTPowerOnTime=
=3D50us
> > > >         L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
> > > >                    T_CommonMode=3D45us LTR1.2_Threshold=3D101376ns
> > > >         L1SubCtl2: T_PwrOn=3D50us
> > > >
> > > > 10000:e1:00.0 Non-Volatile memory controller: Sandisk Corp WD Blue =
SN550
> > > > NVMe
> > > > SSD (rev 01) (prog-if 02 [NVM Express])
> > > >     ...
> > > >     Capabilities: [900 v1] L1 PM Substates
> > > >         L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
> > > > L1_PM_Substates+
> > > >                   PortCommonModeRestoreTime=3D32us PortTPowerOnTime=
=3D10us
> > > >         L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
> > > >                    T_CommonMode=3D0us LTR1.2_Threshold=3D0ns
> > > >         L1SubCtl2: T_PwrOn=3D10us
> > > >
> > > > According to "PCIe r6.0, sec 5.5.4", before enabling ASPM L1.2 on t=
he PCIe
> > > > Root Port and the child NVMe, they should be programmed with the sa=
me
> > > > LTR1.2_Threshold value. However, they have different values in this=
 case.
> > > >
> > > > Invoke aspm_calc_l12_info() to program the L1.2 parameters properly=
 before
> > > > enable L1.2 bits of L1 PM Substates Control Register in
> > > > __pci_enable_link_state().
> > > >
> > > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D218394
> > > > Signed-off-by: Jian-Hong Pan <jhp@endlessos.org>
> > > > ---
> > > > v2:
> > > > - Prepare the PCIe LTR parameters before enable L1 Substates
> > > >
> > > > v3:
> > > > - Only enable supported features for the L1 Substates part
> > > >
> > > > v4:
> > > > - Focus on fixing L1.2 parameters, instead of re-initializing whole=
 L1SS
> > > >
> > > > v5:
> > > > - Fix typo and commit message
> > > > - Split introducing aspm_get_l1ss_cap() to "PCI/ASPM: Introduce
> > > >   aspm_get_l1ss_cap()"
> > > >
> > > >  drivers/pci/pcie/aspm.c | 12 ++++++++++++
> > > >  1 file changed, 12 insertions(+)
> > > >
> > > > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> > > > index c55ac11faa73..553327dee991 100644
> > > > --- a/drivers/pci/pcie/aspm.c
> > > > +++ b/drivers/pci/pcie/aspm.c
> > > > @@ -1402,6 +1402,8 @@ EXPORT_SYMBOL(pci_disable_link_state);
> > > >  static int __pci_enable_link_state(struct pci_dev *pdev, int state=
, bool
> > > > locked)
> > > >  {
> > > >         struct pcie_link_state *link =3D pcie_aspm_get_link(pdev);
> > > > +       struct pci_dev *child =3D link->downstream, *parent =3D lin=
k->pdev;
> > > > +       u32 parent_l1ss_cap, child_l1ss_cap;
> > > >
> > > >         if (!link)
> > > >                 return -EINVAL;
> > > > @@ -1433,6 +1435,16 @@ static int __pci_enable_link_state(struct pc=
i_dev
> > > > *pdev, int state, bool locked)
> > > >                 link->aspm_default |=3D ASPM_STATE_L1_1_PCIPM |
> > > > ASPM_STATE_L1;
> > > >         if (state & PCIE_LINK_STATE_L1_2_PCIPM)
> > > >                 link->aspm_default |=3D ASPM_STATE_L1_2_PCIPM |
> > > > ASPM_STATE_L1;
> > > > +       /*
> > > > +        * Ensure L1.2 parameters: Common_Mode_Restore_Times, T_POW=
ER_ON
> > > > and
> > > > +        * LTR_L1.2_THRESHOLD are programmed properly before enable=
 bits
> > > > for
> > > > +        * L1.2, per PCIe r6.0, sec 5.5.4.
> > > > +        */
> > > > +       if (state & link->aspm_capable & ASPM_STATE_L1_2_MASK) {
> > >
> > > This is still mixing PCIE_LINK_STATE flags with ASPM_STATE flags.
> >
> > Thanks for your review, but I notice some description in PCIe spec,
> > 5.5.4 L1 PM Substates Configuration:
> > "Prior to setting either or both of the enable bits for L1.2, the
> > values for TPOWER_ON, Common_Mode_Restore_Time, and, if the ASPM L1.2
> > Enable bit is to be Set, the LTR_L1.2_THRESHOLD (both Value and Scale
> > fields) must be programmed." =3D> I think this includes both "ASPM L1.2
> > Enable" and "PCI-PM L1.2 Enable" bits.
>
> That's fine. While the spec clearly calls out the ASPM L1.2 Enable bit he=
re, I
> see no harm in including PCI-PM L1.2 in that check. This is what the code
> already does in aspm_l1ss_init().
>
> The issue is the mixed used of two different types of flags that don't ha=
ve the
> same meaning. 'state' contains PCIE_LINK_STATE flags which are part of th=
e
> caller API to the pci_<enabled/disable>_link_state() functions. The ASPM_=
STATE
> flags are used internally to aspm.c to track all states and their meaning=
ful
> combinations such as ASPM_STATE_L1_2_MASK which includes ASPM L1.2 and PC=
I-PM
> L1.2. You should not do bit operations between them.
>
> Also, you should not require that the timings be calculated only if L1_2 =
is
> enabled. You should calculate the timings as long as it's capable. This i=
s also
> what aspm_l1ss_init() does.
>
> The confusion might be over the fact that you are having
> __pci_enable_link_state() call aspm_calc_l12_info(). This should have bee=
n
> handled during initialization of the link in aspm_l1ss_init() and I'm not=
 sure
> why it didn't. Maybe it's because, for VMD, ASPM default state would have
> started out all disabled and this somehow led to aspm_l1ss_init() not get=
ting
> called. But looking through the code I don't see it. It would be great if=
 you
> can confirm why they weren't calculated before.

I debug it again.  If I delete the pci_reset_bus() in vmd controller like:

diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
index 87b7856f375a..39bfda4350bf 100644
--- a/drivers/pci/controller/vmd.c
+++ b/drivers/pci/controller/vmd.c
@@ -930,25 +930,6 @@ static int vmd_enable_domain(struct vmd_dev *vmd,
unsigned long features)
        pci_scan_child_bus(vmd->bus);
        vmd_domain_reset(vmd);

-       /* When Intel VMD is enabled, the OS does not discover the Root Por=
ts
-        * owned by Intel VMD within the MMCFG space. pci_reset_bus() appli=
es
-        * a reset to the parent of the PCI device supplied as argument. Th=
is
-        * is why we pass a child device, so the reset can be triggered at
-        * the Intel bridge level and propagated to all the children in the
-        * hierarchy.
-        */
-       list_for_each_entry(child, &vmd->bus->children, node) {
-               if (!list_empty(&child->devices)) {
-                       dev =3D list_first_entry(&child->devices,
-                                              struct pci_dev, bus_list);
-                       ret =3D pci_reset_bus(dev);
-                       if (ret)
-                               pci_warn(dev, "can't reset device: %d\n", r=
et);
-
-                       break;
-               }
-       }
-
        pci_assign_unassigned_bus_resources(vmd->bus);

        pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features);

Although PCI-PM_L1.2 is disabled, both PCI bridge and the NVMe's
LTR1.2_Threshold are configured as 101376ns:

10000:e0:06.0 PCI bridge [0604]: Intel Corporation 11th Gen Core
Processor PCIe Controller [8086:9a09] (rev 01) (prog-if 00 [Normal
decode])
..
  Capabilities: [200 v1] L1 PM Substates
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates=
+
    PortCommonModeRestoreTime=3D45us PortTPowerOnTime=3D50us
  L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
     T_CommonMode=3D45us LTR1.2_Threshold=3D101376ns
  L1SubCtl2: T_PwrOn=3D50us

10000:e1:00.0 Non-Volatile memory controller [0108]: Sandisk Corp WD
Blue SN550 NVMe SSD [15b7:5009] (rev 01) (prog-if 02 [NVM Express])
..
  Capabilities: [900 v1] L1 PM Substates
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates=
+
    PortCommonModeRestoreTime=3D32us PortTPowerOnTime=3D10us
  L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
     T_CommonMode=3D0us LTR1.2_Threshold=3D101376ns
  L1SubCtl2: T_PwrOn=3D50us

Then, I apply the patch "PCI: vmd: Set PCI devices to D0 before enable
PCI PM's L1 substates".  Both PCI bridge and the NVMe's PCI-PM_L1.2 is
enabled and LTR1.2_Threshold is configured as 101376ns.

10000:e0:06.0 PCI bridge [0604]: Intel Corporation 11th Gen Core
Processor PCIe Controller [8086:9a09] (rev 01) (prog-if 00 [Normal
decode])
..
  Capabilities: [200 v1] L1 PM Substates
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates=
+
    PortCommonModeRestoreTime=3D45us PortTPowerOnTime=3D50us
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
     T_CommonMode=3D45us LTR1.2_Threshold=3D101376ns
  L1SubCtl2: T_PwrOn=3D50us

10000:e1:00.0 Non-Volatile memory controller [0108]: Sandisk Corp WD
Blue SN550 NVMe SSD [15b7:5009] (rev 01) (prog-if 02 [NVM Express])
..
  Capabilities: [900 v1] L1 PM Substates
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates=
+
    PortCommonModeRestoreTime=3D32us PortTPowerOnTime=3D10us
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
     T_CommonMode=3D0us LTR1.2_Threshold=3D101376ns
  L1SubCtl2: T_PwrOn=3D50us

I do not know VMD very much.  However, from the test result, it looks
like LTR1.2_Threshold has been configured properly originally.  But,
LTR1.2_Threshold is misconfigured by 'pci_reset_bus()'.

Jian-Hong Pan


> >
> > Jain-Hong Pan
> >
> > > 'state' should not even matter.
> > > The timings should always be calculated and programmed as long
> > > as L1_2 is capable. That way the timings are ready even if L1_2 isn't=
 being
> > > enabled now (in case the user enables it later).
> > >
> > > David
> > >
> > > > +               parent_l1ss_cap =3D aspm_get_l1ss_cap(parent);
> > > > +               child_l1ss_cap =3D aspm_get_l1ss_cap(child);
> > > > +               aspm_calc_l12_info(link, parent_l1ss_cap, child_l1s=
s_cap);
> > > > +       }
> > > >         pcie_config_aspm_link(link, policy_to_aspm_state(link));
> > > >
> > > >         link->clkpm_default =3D (state & PCIE_LINK_STATE_CLKPM) ? 1=
 : 0;
> > >
>