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Date: Fri, 3 May 2024 10:21:19 -0700
From: Dan Williams <dan.j.williams@intel.com>
To: Ira Weiny <ira.weiny@intel.com>, Jonathan Cameron
	<Jonathan.Cameron@huawei.com>
CC: Dave Jiang <dave.jiang@intel.com>, Fan Ni <fan.ni@samsung.com>, "Navneet
 Singh" <navneet.singh@intel.com>, Dan Williams <dan.j.williams@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>, Alison Schofield
	<alison.schofield@intel.com>, Vishal Verma <vishal.l.verma@intel.com>,
	<linux-btrfs@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 07/26] cxl/port: Add dynamic capacity size support to
 endpoint decoders
Message-ID: <66351d0f9ac2e_1aefb29492@dwillia2-mobl3.amr.corp.intel.com.notmuch>
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Ira Weiny wrote:
> > >  	else
> > >  		free_pmem_start = cxlds->pmem_res.start;
> > >  
> > > +	/*
> > > +	 * Limit each decoder to a single DC region to map memory with
> > > +	 * different DSMAS entry.
> 
> This prevents more than 1 region per DC partition (region).

Why? Multiple regions per partition is the current status quo for other
partition types.

> > I notice in the pmem equivalent there is a case for part of the region already mapped.
> > Can that not happen for a DC region as well?
> 
> See above check.  Each DC region (partition) was to be associated with a
> single DSMAS entry.  I'm unclear now why that decision was made.

The limitation of one DSMAS per partition makes sense otherwise that
would indicate performance across different spans of the partition.

> It does not seem hard to add this though.  Do we really need that ability
> considering dax devices are likely going to be the main boundry for users
> of a DC region?

It seems like extra work to make DCD a special case compared to the
other partition types, so the burden of proof is the other way. Why
tolerate DCD divergence from the status quo?