Received-SPF: pass (google.com: domain of linux-kernel+bounces-168473-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Date: Sat, 04 May 2024 08:49:07 +0800
Subject: [PATCH 14/18] clk: imx: imx8qxp: Add LVDS bypass clocks
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Message-Id: <20240504-imx-clk-v1-14-f7915489d58d@nxp.com>
References: <20240504-imx-clk-v1-0-f7915489d58d@nxp.com>
In-Reply-To: <20240504-imx-clk-v1-0-f7915489d58d@nxp.com>
To: Abel Vesa <abelvesa@kernel.org>, 
 Michael Turquette <mturquette@baylibre.com>, 
 Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>, 
 Sascha Hauer <s.hauer@pengutronix.de>, 
 Pengutronix Kernel Team <kernel@pengutronix.de>, 
 Fabio Estevam <festevam@gmail.com>, Jacky Bai <ping.bai@nxp.com>, 
 Ye Li <ye.li@nxp.com>, Dong Aisheng <aisheng.dong@nxp.com>
Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, 
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 
 Abel Vesa <abel.vesa@linaro.org>, Peng Fan <peng.fan@nxp.com>, 
 Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>, 
 "Oliver F. Brown" <oliver.brown@oss.nxp.com>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-MessageSentRepresentingType: 1
X-MS-PublicTrafficType: Email
X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|PA4PR04MB7726:EE_
X-MS-Office365-Filtering-Correlation-Id: 25acf670-d556-4736-2b13-08dc6bd30dce
X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True
X-MS-Exchange-SenderADCheck: 1
X-MS-Exchange-AntiSpam-Relay: 0
X-Microsoft-Antispam:
	BCL:0;ARA:13230031|7416005|52116005|366007|1800799015|376005|921011|38350700005;
X-Microsoft-Antispam-Message-Info:
	=?utf-8?B?dGN5MG1mRy93Q3p0TW9zQUhaekNVb0MrcUM2dTVxZDMva1dmazIyWXFJNHli?=
 =?utf-8?B?UjMrdmRKZDN1d3FOQ1ZnTE5EU0EvQlZCSDlRcEZRSXI1R0JxTjJMeFJaSWx3?=
 =?utf-8?B?bm80bkxNRVVUOXI5QUVxWnJlNkxtTUM5NzZwWjZ3cU1ZSW9FOVBZeFVtQ05Q?=
 =?utf-8?B?Z1p5NWp5VHIzVXRGWGxWd0VoTEJBR2EvaE9pVWpma20zZGlzOGM1Uk9TQkVm?=
 =?utf-8?B?bGtLcUwva0xsMlJoeE5zOXNqZ3lmd0YyS09UVDRLdnlzM05BUWwxVU11Z29x?=
 =?utf-8?B?WEFiNUJYbytjUTJsYnVHSDZHQUgxbnN0MS9GSXIrL0dLVVJaQ080bmViYVh1?=
 =?utf-8?B?bnl5ZFJUaHZZQ2IxdW5adEk1WUFrTUhTY3hnRXJYZXNLZHRCOGdib29FOVE5?=
 =?utf-8?B?OXVQVkJIK1R0cWN2MnlOL20xV1QrT3lDRWNQOFo2elZhWlltRFdNUHB1MzB0?=
 =?utf-8?B?U2Ivd1h4Q3RlQngxajBjM0hnVW1iSENzd1hrcDI1cTQyNjZ2ZFplNTVkMDNi?=
 =?utf-8?B?YzU1cnZqdytzamV5ZFM0VFVpcWxod1VVWHJUcndXVWJyVHgxOVFmVUYwYnRX?=
 =?utf-8?B?MTRGYzlRSlVvS1MrRGkrN0ovcW1oOUJRdzN0WUtXbTR6ZEFiZW1rRlpwbjl0?=
 =?utf-8?B?WGtxVURQdFhrb1JSK1dta08zcHNTdlR4alM5L2w1WTMrVEo2b2hmWitmQlZY?=
 =?utf-8?B?OVI3YXRVWG1uSmpQVTlNOWs0cVlwN0d0OVVJajBoMllOaWt0RVVkeENsWlFS?=
 =?utf-8?B?ZFpkS3Q5MUhtVTJNT2N4MnBmSlRxeHk4eTAxdTZSNDFTbjZIaWZOZEZQRjM2?=
 =?utf-8?B?U0FKcW5CejBUR1hVVHRxeG9vOW5CbzhEUHEybHRVclE2VDNuSnBFMDlNQ2NE?=
 =?utf-8?B?Z1VucU16UVVZckE2bWQvOStFaWtDSG5tN2Q5QloybTFIaXdBdzdsMDBUTWli?=
 =?utf-8?B?NktVUzJOV3luR3lzQ1EvejM2UGtHdUlOemNKdjhiM002KzhMT0t4WUNaRlV0?=
 =?utf-8?B?ODlBeXBhUjRLMjgrS20ybTZLaTlwdmYwOFhndkZ3S0FVUXh0TVFBci9hTklu?=
 =?utf-8?B?cS9OMVVaN010Vzl4SE85Q0l3UW5UVVMzNFNPcjhPVWhWU1luZGF4T2J4dTA0?=
 =?utf-8?B?T3U3RUtuRm5VT0RtOWpyYURwdlY4WEh3c3lPMGFEYWlSamI1QWlWK2M4N3h0?=
 =?utf-8?B?Rk04R0IzcnpaemxqZW4zcTBmbG5sZ2tJeUJFWm0vMEp0QzhROEhhMml0WXdL?=
 =?utf-8?B?UEdocnQyUk1RazVnZGpja1U2K2l0U0FiN3FOR3R6RTROVzkyM2trU2NJVFYz?=
 =?utf-8?B?ZTl5VExicDlJMExwMlR3b2wxL0VmaXJkaWJXSmxSUGVvMHBQWGswSUdWNXVa?=
 =?utf-8?B?ZjJHUFd5aFI0TVRnb1l2ZGJYaVJySEp4ZTh5dTl2b2wvSU9TQWpDN0MrWGxz?=
 =?utf-8?B?VDNwRDU3UXd4eFB1Z0t6aDRSRDU1V3N1YjVlRk05N3hoYk5HN3Zrb3BJd09p?=
 =?utf-8?B?R1dPeE8zaHJlTzRkUFFSd2JVMGI0WEtHUFIvak5zU0sydEJvUHpvY3dkTEpt?=
 =?utf-8?B?SEhVTDg2QTYwKzNId2VmRVJZY3U4MUJhK2J2ZEljWTExWVR4UzBMWWwxaG05?=
 =?utf-8?B?eFhOYzhnQVhDNWxHbVd0ZHpBZ1RzNThhWE9jOEF0TkVLZjFuc0FnUVlSMm50?=
 =?utf-8?B?Q3RCNHhNcDV0aFAvSkFKbnEwK0VXVEw5cmkzVHR4akRqUlFnSHlEdXZrRmlt?=
 =?utf-8?B?eEVUU09xTlJHYTl5QmU4SXNTM2doQVBLVzhhNUw0ZXRFV0tLMlNjMzBaNTlI?=
 =?utf-8?Q?pFXX0frrWuEv1crbhgq87a8IovJF5MI/2Ta14=3D?=
X-Forefront-Antispam-Report:
	CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9417.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(7416005)(52116005)(366007)(1800799015)(376005)(921011)(38350700005);DIR:OUT;SFP:1101;
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?utf-8?B?RHR4TEFzL3AyVGMwdjRJSEREQ3NFanlvUHhieEhCNHpFKy9pK2JNdStGUHVa?=
 =?utf-8?B?TGh2dTd1VC9SRXRRZXpoUEF1c05ibnVoRFc4QUhPbVZnMzVRRHhVaUJwQ3dS?=
 =?utf-8?B?WWZVVzVmMURzNndDZ2JOZHZqZDQxYlljSXpVUHpKVG14MGhLeGJ3N1JwTTdm?=
 =?utf-8?B?V1gvaUQyaGtUK2hMcGpyLzZvcitJeFdTcGhleklnc3M5bUxhL1pYTi93d29D?=
 =?utf-8?B?ajFIRVpuUjFOUEkwZmx2VUFaWXpWc3FXZ0lMVEw0OHZVbFF4MGRIdHV2Ykpw?=
 =?utf-8?B?ZFpTZ2tldWpuQngwVkk5MGd1bmRtVmZ4SVRvS05rYTE3a01BWGxFTWdta1Vp?=
 =?utf-8?B?QXB5TERwWE1nSklIT1VYcVdDMGs5UFRXZ2VGVzgrTUlneHVla0xqaHZnWXdj?=
 =?utf-8?B?SCs0WTJPb1lmd3huWlBZMUdoK1JpUVRzM1BOY0tpVEN0dTI4dldiS2J3QTJB?=
 =?utf-8?B?aUMwZXdORzBuZGtKRFV5eEphVnc4Q3NRUFBlMm1sSXY2VEQ0TmNQV3lGclpR?=
 =?utf-8?B?dWFHdEgyYTZFeDFob2V2bDF0RU9rUVI2bUgvOGlMZWMwRzNOUDBLaGYwSWFx?=
 =?utf-8?B?RWRWVVh6MDRJS09TWEttQ3FKZEZCRks5bDlkZEdHZ1V2Sk5MWU54bzJQSEoz?=
 =?utf-8?B?Z0hzZ1djNk84WFVrWFRaNjFuSk9yYWhCM2lWbnBubGlZRzlPNFc5Tm5lSmVR?=
 =?utf-8?B?NzZ5QjlSY2tpUjJVcW0wdm5pNGpHWG43dHVCVG56YU9wR3VVb3M5eUZ3N1dM?=
 =?utf-8?B?NW9WSGpkcEpqVDNRMk50SFdsZUFtbXgzZVdPSk4zUllVM3dydzMvZWE2MnF0?=
 =?utf-8?B?QUMxZmtEa0szUHNOQUZsaldFNUkwc1hTVy8rUERqdXlhQkhyaXZLdGRJbGRN?=
 =?utf-8?B?UWV6RzVYMTl4b0R1UGV2REJnVUswcWJwdTQ3azM5MXU1ekpxQ3R1ODg1NnBW?=
 =?utf-8?B?a0NReEY3VGE4djdaUmRIN1cvd1NQbVF6b0FleHNXeEFaWDEyc3lWcm9IQ2pk?=
 =?utf-8?B?ai9OVzNKN0k4RFVXOWRFNUJjYXNHaXltS1BEeUtpcDhOR1NSTW5yQk5qMXdh?=
 =?utf-8?B?TjlyVS9lRXRYUXF0Vk1LL0pYNHd0Yk9TL3pnS0NpNzRUeURsTG9aTGcwajFZ?=
 =?utf-8?B?amIzMVFmeTVEempCQTI5bE1UK2dFRUQ0UG80d2ZmZFIzenlhc3hJVTk0RStz?=
 =?utf-8?B?Y1ZOcEFQbHpUeGFEM2lFK0h1dmJrbHBpY1Z1RFA2d3cvT0VQUUFDQnc4cUFn?=
 =?utf-8?B?cG8xNlVteTk3OFBoMUord1RmUFNMZk9yTzNvckpzWjhseGlndTk0NmhPQW1x?=
 =?utf-8?B?MklIZTlMU2VMcDhRKzFyRzZJYTRBbkwwblBRQkNrSFR6TmtXUFJTRHNwajRh?=
 =?utf-8?B?REtqRHRtSGk5d0ZXc0xZSTJTR1pnS1ZlcVZFU0dMNU1EVklmejBHRjJDQWM1?=
 =?utf-8?B?dzVORkxsei9zejllS0U3MmFkL1p0V2w1NTVYanRxNWwrUnZCS0V4N3Y0a2lS?=
 =?utf-8?B?VEI1b0p5OG5pT0J0NDdKYThhWWM0aWh1Q28vbGVoeGZyRU1MMzJEVFJxenAv?=
 =?utf-8?B?OWROaGtkM1I0Q0w5eGhXaktHdVdGQWFxYXZBL0Z2cnp1dFVzM3M5SnVLeXpm?=
 =?utf-8?B?NURYNXhJWnVsaG1IWjhuRXAzUTY3U1pnNVg2TXdtdXlNQm1yZUhPczVRUmpF?=
 =?utf-8?B?TE5zbk1UeGtMUWJrVFFUMDdwSEE5SjZ2T1dsN2Z0Q0QwSXJpRThmbnlKS2xV?=
 =?utf-8?B?OEs2dTk3ZlM1OWNJQWNkcjZEOHdTTVM0VnVZUHVHaHplQndQMnhEWGpOalFt?=
 =?utf-8?B?N1NLOEFFSGdOU3RUb3hLd0F2UVZ1QTQvTGtEN0dDTWl6bjh5Z0VkeDRZWVFs?=
 =?utf-8?B?VENVaERxVjFzUWVSWUZ4cWVXc0dtdXQ0YUJXdkh3d2hIYkgwVUVvcEhuc1lU?=
 =?utf-8?B?dW92QzRBc3ZRbFBoRVpjY1dGQlNiQU5XejBXdDVDY2ZJVFVIVXZuaXZ2MCtm?=
 =?utf-8?B?NWtlTmVubGdNZ0xScklHc2FKMGQ3SGVFZTU0b1g5N0tLRnQ1SU45Ty9US0hn?=
 =?utf-8?B?RXdJaWM5OTN4RTJac3RNNk82ZWVDN0J5aVVKcDBmYkI3eWJWdW9xN2ovMFM4?=
 =?utf-8?Q?X7TRCaFnMCadBnk2pW2x3hwak?=
X-OriginatorOrg: oss.nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 25acf670-d556-4736-2b13-08dc6bd30dce
X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2024 00:42:19.4468
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: Nar6kjVz76042Qeht6jW9yLogXZJTDH0TrHNWUOxhkQ5iv3/auRDJFf1Q5sT/Wqt0sOVnFBSVw1V+RbYPCBxtQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR04MB7726

From: Peng Fan <peng.fan@nxp.com>

For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS
clocks with imx_clk_scu2 as the parent needs to explicitly set.

In order to make sure MIPI DSI works well after suspend/resume, the LVDS
pixel and phy clocks must be initialized before the MIPI tx_esacpe
and rx_escape clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all
on the same MSLICE. They all share the same clock parent. So, setting the
parent source or rate affects all of these clocks. In the LVDS use case the
MIPI tx_escape and rx_escape are not saved and restored. So, LVDS works for
either clock initialization order. For MIPI case, LVDS must be initialized first.

Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 7d8883916cac..a0654edaae83 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -71,7 +71,7 @@ static const char *const lvds0_sels[] = {
 	"clk_dummy",
 	"clk_dummy",
 	"clk_dummy",
-	"mipi0_lvds_bypass_clk",
+	"lvds0_bypass_clk",
 };
 
 static const char *const lvds1_sels[] = {
@@ -79,7 +79,7 @@ static const char *const lvds1_sels[] = {
 	"clk_dummy",
 	"clk_dummy",
 	"clk_dummy",
-	"mipi1_lvds_bypass_clk",
+	"lvds1_bypass_clk",
 };
 
 static const char * const mipi_sels[] = {
@@ -223,9 +223,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	/* MIPI-LVDS SS */
 	imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);
 	imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
-	imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
-	imx_clk_scu2("mipi0_lvds_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
-	imx_clk_scu2("mipi0_lvds_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
+	imx_clk_scu("lvds0_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu2("lvds0_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu2("lvds0_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
 	imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);
 	imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);
 	imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
@@ -235,10 +235,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 
 	imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);
 	imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
-	imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
-	imx_clk_scu2("mipi1_lvds_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
-	imx_clk_scu2("mipi1_lvds_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
-
+	imx_clk_scu("lvds1_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu2("lvds1_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu2("lvds1_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
 	imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);
 	imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);
 	imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY);

-- 
2.37.1