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03 May 2024 19:06:47 -0700 Message-ID: Date: Sat, 4 May 2024 10:05:14 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: baolu.lu@linux.intel.com, Palmer Dabbelt , Albert Ou , Anup Patel , Sunil V L , Nick Kossifidis , Sebastien Boeuf , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com Subject: Re: [PATCH v4 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver To: Tomasz Jeznach , Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley References: <68afb8d5e45e82dfc818385e01e9ddaa659007e1.1714752293.git.tjeznach@rivosinc.com> Content-Language: en-US From: Baolu Lu In-Reply-To: <68afb8d5e45e82dfc818385e01e9ddaa659007e1.1714752293.git.tjeznach@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 5/4/24 12:12 AM, Tomasz Jeznach wrote: > Introduce platform device driver for implementation of RISC-V IOMMU > architected hardware. > > Hardware interface definition located in file iommu-bits.h is based on > ratified RISC-V IOMMU Architecture Specification version 1.0.0. > > This patch implements platform device initialization, early check and > configuration of the IOMMU interfaces and enables global pass-through > address translation mode (iommu_mode == BARE), without registering > hardware instance in the IOMMU subsystem. > > Link:https://github.com/riscv-non-isa/riscv-iommu > Co-developed-by: Nick Kossifidis > Signed-off-by: Nick Kossifidis > Co-developed-by: Sebastien Boeuf > Signed-off-by: Sebastien Boeuf > Signed-off-by: Tomasz Jeznach Reviewed-by: Lu Baolu Best regards, baolu