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From: Peng Fan <peng.fan@nxp.com>
To: Francesco Dolcini <francesco@dolcini.it>, "Peng Fan (OSS)"
	<peng.fan@oss.nxp.com>
CC: Abel Vesa <abelvesa@kernel.org>, Michael Turquette
	<mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Shawn Guo
	<shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>,
	Jacky Bai <ping.bai@nxp.com>, Ye Li <ye.li@nxp.com>, Aisheng Dong
	<aisheng.dong@nxp.com>, "linux-clk@vger.kernel.org"
	<linux-clk@vger.kernel.org>, "imx@lists.linux.dev" <imx@lists.linux.dev>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>, Abel Vesa <abel.vesa@linaro.org>
Subject: RE: [PATCH 10/18] clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux
 for i.MX7D
Thread-Topic: [PATCH 10/18] clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux
 for i.MX7D
Thread-Index: AQHanbveZhJbbEOK1EWGUWEQAnsbdLGG+hoAgAAUHOA=
Date: Sat, 4 May 2024 13:15:02 +0000
Message-ID:
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References: <20240504-imx-clk-v1-0-f7915489d58d@nxp.com>
 <20240504-imx-clk-v1-10-f7915489d58d@nxp.com>
 <20240504120124.GC3666@francesco-nb>
In-Reply-To: <20240504120124.GC3666@francesco-nb>
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> Subject: Re: [PATCH 10/18] clk: imx: Remove CLK_SET_PARENT_GATE for
> DRAM mux for i.MX7D
>=20
> Hello Peng,
>=20
> On Sat, May 04, 2024 at 08:49:03AM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > For i.MX7D DRAM related mux clock, the clock source change should ONLY
> > be done done in low level asm code without accessing DRAM, and then
> > calling clk API to sync the HW clock status with clk tree, it should
> > never touch real clock source switch via clk API, so
> > CLK_SET_PARENT_GATE flag should NOT be added, otherwise, DRAM's clock
> > parent will be disabled when DRAM is active, and system will hang.
>=20
> From the description this is solving a system hang, but no fixes tag nor =
cc
> stable.

Not add fixes tab, because current upstream kernel not support DRAM freq
update for 7D, so the issue will not happen in upstream kernel. But in case
in future DRAM freq change needs change..
>=20
> Francesco