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From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Ilpo =?utf-8?Q?J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>,
 linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>, Lorenzo
 Pieralisi <lorenzo.pieralisi@arm.com>, Rob Herring <robh@kernel.org>,
 Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>, Andrew Lunn
 <andrew@lunn.ch>,
 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Russell King
 <linux@armlinux.org.uk>, linux-arm-kernel@lists.infradead.org,
 linux-kernel@vger.kernel.org
Cc: Ilpo =?utf-8?Q?J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>
Subject: Re: [PATCH 04/10] ARM: orion5x: Use generic PCI Conf Type 1 helper
In-Reply-To: <20240429104633.11060-5-ilpo.jarvinen@linux.intel.com>
References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com>
 <20240429104633.11060-5-ilpo.jarvinen@linux.intel.com>
Date: Sun, 05 May 2024 18:39:00 +0200
Message-ID: <87msp4nrh7.fsf@BLaptop.bootlin.com>
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Ilpo J=C3=A4rvinen <ilpo.jarvinen@linux.intel.com> writes:

> Convert orion5x PCI code to use pci_conf1_ext_addr() from PCI core to
> calculate PCI Configuration Type 1 address.
>
> Signed-off-by: Ilpo J=C3=A4rvinen <ilpo.jarvinen@linux.intel.com>

Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>

As some other patches of the series depend on patches in the PCIe
subsystem, the best approach would be to let you apply the series
through the PCIe subsystem.

Thanks,

Gregory

> ---
>  arch/arm/mach-orion5x/pci.c | 17 ++---------------
>  1 file changed, 2 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
> index 6376e1db6386..8b7d67549adf 100644
> --- a/arch/arm/mach-orion5x/pci.c
> +++ b/arch/arm/mach-orion5x/pci.c
> @@ -216,15 +216,6 @@ static int __init pcie_setup(struct pci_sys_data *sy=
s)
>  #define PCI_P2P_DEV_OFFS		24
>  #define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)
>=20=20
> -/*
> - * PCI_CONF_ADDR bits
> - */
> -#define ORION5X_PCI_CONF_REG(reg)	((reg) & 0xfc)
> -#define ORION5X_PCI_CONF_FUNC(func)	(((func) & 0x3) << 8)
> -#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
> -#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
> -#define PCI_CONF_ADDR_EN		(1 << 31)
> -
>  /*
>   * Internal configuration space
>   */
> @@ -276,9 +267,7 @@ static int orion5x_pci_hw_rd_conf(int bus, u8 devfn, =
u32 where,
>  	unsigned long flags;
>  	spin_lock_irqsave(&orion5x_pci_lock, flags);
>=20=20
> -	writel(PCI_CONF_BUS(bus) |
> -		PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) |
> -		ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_AD=
DR);
> +	writel(pci_conf1_addr(bus, devfn, where, true), PCI_CONF_ADDR);
>=20=20
>  	*val =3D readl(PCI_CONF_DATA);
>=20=20
> @@ -300,9 +289,7 @@ static int orion5x_pci_hw_wr_conf(int bus, u8 devfn, =
u32 where,
>=20=20
>  	spin_lock_irqsave(&orion5x_pci_lock, flags);
>=20=20
> -	writel(PCI_CONF_BUS(bus) |
> -		PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) |
> -		ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_AD=
DR);
> +	writel(pci_conf1_addr(bus, devfn, where, true), PCI_CONF_ADDR);
>=20=20
>  	if (size =3D=3D 4) {
>  		__raw_writel(val, PCI_CONF_DATA);
> --=20
> 2.39.2